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ORCIDAzam Seyedi
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2020 – today
- 2022
[j2]Azam Seyedi
, Snorre Aunet, Per Gunnar Kjeldsberg:
Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements. IEEE Access 10: 30624-30642 (2022)
2010 – 2019
- 2019
- [c7]Azam Seyedi, Snorre Aunet, Per Gunnar Kjeldsberg:
Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. NORCAS 2019: 1-6 - 2016
- [b1]Azam Seyedi:
Circuit designs for increasing reliability and reducing energy. Polytechnic University of Catalonia, Spain, 2016 - 2015
- [c6]Azam Seyedi, Vasileios Karakostas, Stefan Cosemans, Adrián Cristal, Mario Nemirovsky, Osman S. Unsal:
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs. NANOARCH 2015: 51-56 - 2014
- [c5]Gulay Yalcin, Azam Seyedi, Osman S. Unsal, Adrián Cristal:
Flexicache: Highly Reliable and Low Power Cache under Supply Voltage Scaling. CARLA 2014: 173-190 - 2013
- [c4]Azam Seyedi, Gulay Yalcin, Osman S. Unsal, Adrián Cristal:
Circuit design of a novel adaptable and reliable L1 data cache. ACM Great Lakes Symposium on VLSI 2013: 333-334 - 2012
- [j1]Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache. Integr. 45(3): 237-245 (2012) - [c3]Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP 2012: 1-6 - 2011
- [c2]Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371 - [c1]Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI 2011: 325-330
Coauthor Index
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