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ORCIDJ. Rubén Titos Gil
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2020 – today
- 2024
[j16]Víctor Nicolás-Conesa
, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems 104: 104975 (2024)- [c19]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Alberto Ros:
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO 2024: 840-855 - 2022
- [j15]Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean:
Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. 78(1): 919-944 (2022) - [j14]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 33(1): 1-13 (2022) - [c18]Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP 2022: 157-164 - 2021
- [c17]Eduardo José Gómez-Hernández, Juan M. Cebrian, J. Rubén Titos Gil, Stefanos Kaxiras, Alberto Ros:
Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. MICRO 2021: 337-349 - 2020
- [j13]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. 145: 111-123 (2020) - [j12]J. Rubén Titos Gil, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 31(6): 1301-1315 (2020)
2010 – 2019
- 2019
- [j11]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio:
Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. 30(11): 2608-2623 (2019) - 2017
- [c16]J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández Pascual, Alberto Ros, Manuel E. Acacio:
Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS 2017: 20:1-20:10 - 2016
- [j10]J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal:
Architectural support for efficient message passing on shared memory multi-cores. J. Parallel Distributed Comput. 95: 92-106 (2016) - [c15]Oscar Palomar, Santhosh Kumar Rethinagiri, Gulay Yalcin, J. Rubén Titos Gil, Pablo Prieto, Emma Torrella, Osman S. Unsal, Adrián Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier, Dragomir Milojevic:
Energy minimization at all layers of the data center: The ParaDIME project. DATE 2016: 684-689 - 2015
- [j9]Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Gulay Yalcin, Thomas Knauth, J. Rubén Titos Gil, Pablo Prieto, Malte Schneegaß, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Dragomir Milojevic:
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers. Microprocess. Microsystems 39(8): 1174-1189 (2015) - [c14]J. Rubén Titos Gil, Oscar Palomar, Osman S. Unsal, Adrián Cristal:
DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores. ICPP 2015: 130-139 - [c13]Jochen Hollmann, J. Rubén Titos Gil, Per Stenström:
Enhancing Garbage Collection Synchronization Using Explicit Bit Barriers. ICPP 2015: 769-778 - [r1]J. Rubén Titos Gil, Manuel E. Acacio:
Hardware Approaches to Transactional Memory in Chip Multiprocessors. Handbook on Data Centers 2015: 805-835 - 2014
- [j8]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems. J. Supercomput. 68(2): 914-934 (2014) - [j7]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 25(5): 1359-1369 (2014) - [c12]Bhavishya Goel, J. Rubén Titos Gil, Anurag Negi, Sally A. McKee, Per Stenström:
Performance and Energy Analysis of the Restricted Transactional Memory Implementation on Haswell. IPDPS 2014: 615-624 - 2013
- [j6]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
On the design of energy-efficient hardware transactional memory systems. Concurr. Comput. Pract. Exp. 25(6): 862-880 (2013) - [j5]Anurag Negi, J. Rubén Titos Gil:
SCIN-cache: Fast speculative versioning in multithreaded cores. ACM Trans. Archit. Code Optim. 9(4): 58:1-58:26 (2013) - [j4]Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal:
Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. 10(4): 42:1-42:25 (2013) - [j3]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(1): 59-71 (2013) - [j2]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
Eager Beats Lazy: Improving Store Management in Eager Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. 24(11): 2192-2201 (2013) - 2012
- [j1]J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero:
Hardware transactional memory with software-defined conflicts. ACM Trans. Archit. Code Optim. 8(4): 31:1-31:20 (2012) - [c11]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152 - [c10]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández:
Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP 2012: 221-228 - 2011
- [c9]Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204 - [c8]Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero:
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT 2011: 361-371 - [c7]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82 - [c6]J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström:
ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62 - [c5]Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström:
The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707 - 2010
- [c4]Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio:
Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD 2010: 9-16
2000 – 2009
- 2009
- [c3]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Speculation-based conflict resolution in hardware transactional memory. IPDPS 2009: 1-12 - 2008
- [c2]J. Rubén Titos Gil, Manuel E. Acacio, José M. García:
Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC 2008: 541-554 - [c1]J. Rubén Titos Gil, Manuel E. Acacio, José Manuel García Carrasco:
Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP 2008: 30-37
Coauthor Index
aka: José Manuel García Carrasco
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