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2010 – 2019
- 2012
[c8]Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Masahiro Takakura:
An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms. Asian Test Symposium 2012: 1- 2011
- [c7]Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer:
Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium 2011: 84-89
2000 – 2009
- 2008
- [c6]Jun Matsushima, Yoichi Maeda, Masahiro Takakura:
CooLBIST: An Effective Approach of Test Power Reduction for LBIST. ATS 2008: 264 - 2004
- [j2]Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Kazuhiko Iwasaki:
Technique to Diagnose Open Defects that Takes Coupling Effects into Consideration. IEICE Trans. Inf. Syst. 87-D(9): 2179-2185 (2004) - 2002
- [c5]Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura:
A Persistent Diagnostic Technique for Unstable Defects. ITC 2002: 242-249 - 2001
- [c4]Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura, Yasuo Sato:
An Approach to Improve the Resolution of Defect-Based Diagnosis. Asian Test Symposium 2001: 123- - 2000
- [j1]Kohtaro Fujimoto, Satoru Kyo, Masahiro Takakura, Taro Kanaya, Yasuhide Kitagawa, Hideaki Itoh, Morinobu Takahashi, Masaki Inoue:
Identification and characterization of negative regulatory elements of the human telomerase catalytic subunit (hTERT) gene promoter: possible role of MZF-2 in transcriptional repression of hTERT. Nucleic Acids Res. 28(13): 2557-2562 (2000)
1990 – 1999
- 1997
- [c3]Kazumi Hatayama, Mitsuji Ikeda, Masahiro Takakura, Satoshi Uchiyama, Yoriyuki Sakamoto:
Application of a Design for Delay Testability Approach to High Speed Logic LSIs. Asian Test Symposium 1997: 112-115 - 1991
- [c2]Yutaka Sekiyama, Yasuyuki Fujihara, Terumine Hayashi, Mitsuho Seki, Jiro Kusuhara, Kazuhiko Iijima, Masahiro Takakura, Koji Fukatani:
Timing-Oriented Routers for PCB Layout Design of High-Performance Computers. ICCAD 1991: 332-335
1980 – 1989
- 1989
- [c1]Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama:
Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989: 161-165
Coauthor Index
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