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ORCIDSunghyun Park 0006
Person information
- affiliation: University of Michigan, Ann Arbor, USA
- not to be confused with: Sunghyun Park 0004
Other persons with the same name
- Sunghyun Park (aka: SungHyun Park, Sung-Hyun Park) — disambiguation page
- Sunghyun Park 0001 — University of Southern California, Los Angeles, CA, USA
- Sunghyun Park 0002 — Massachusetts Institute of Technology, Cambridge, MA, USA
- Sunghyun Park 0003 — Samsung Electronics Co., Ltd., South Korea
- Sunghyun Park 0004 — OctoAI, Seattle, WA, USA (and 1 more)
- Sunghyun Park 0005
![[0009-0006-1056-2826]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0009-0006-1056-2826")
— Yonsei University - Sunghyun Park 0007 — Georgia Tech, Atlanta, GA, USA
- Sunghyun Park 0008 (aka: SungHyun Park 0008) — Soongsil University, Department of Smart Systems Software, Seoul, Korea
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Journal Articles
- 2009
[j4]Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn:
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits 44(10): 2755-2765 (2009)- [j3]JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1807-1817 (2009) - 2007
- [j2]Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. IEEE J. Solid State Circuits 42(9): 1865-1872 (2007) - 2006
- [j1]Sunghyun Park, Michael P. Flynn:
A regenerative comparator structure with integrated inductors. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(8): 1704-1711 (2006)
Conference and Workshop Papers
- 2008
- [c4]JunYoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn:
A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. CICC 2008: 347-350 - 2006
- [c3]Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn:
A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. CICC 2006: 489-492 - [c2]Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4GS/s 4b Flash ADC in 0.18µm CMOS. ISSCC 2006: 2330-2339 - 2005
- [c1]Sunghyun Park, Michael P. Flynn:
Design techniques for high performance CMOS flash analog-to-digital converters. ECCTD 2005: 131-134
Coauthor Index
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