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ORCIDRafael Gadea Gironés
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Journal Articles
- 2023
[j12]Rafael Gadea Gironés
, Jorge D. Fe, José María Monzó:
Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge. Microprocess. Microsystems 98: 104824 (2023)- 2018
- [j11]Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch:
Optimization of Deep Neural Networks Using SoCs with OpenCL. Sensors 18(5): 1384 (2018) - 2015
- [j10]Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés:
Evolutionary optimization of neural networks with heterogeneous computation: study and implementation. J. Supercomput. 71(8): 2944-2962 (2015) - 2011
- [j9]Néstor Ferrando, M. A. Gosálvez, Joaquín Cerdá, Rafael Gadea Gironés, Kazuo Sato:
Octree-based, GPU implementation of a continuous cellular automaton for the simulation of complex, evolving surfaces. Comput. Phys. Commun. 182(3): 628-640 (2011) - 2010
- [j8]Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés:
Approximate k-NN delta test minimization method using genetic algorithms: Application to time series. Neurocomputing 73(10-12): 2017-2029 (2010) - 2008
- [j7]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona:
A Mixed Hardware/Software SOFM Training System. Computación y Sistemas 11(4) (2008) - [j6]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero:
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding. Microprocess. Microsystems 32(1): 33-44 (2008) - 2007
- [j5]Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona:
A wavelet-VQ system for real-time video compression. J. Real Time Image Process. 2(4): 271-280 (2007) - 2006
- [j4]Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero:
An active methodology for teaching electronic systems design. IEEE Trans. Educ. 49(3): 355-359 (2006) - [j3]Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés:
A Novel FPGA Architecture of a 2-D Wavelet Transform. J. VLSI Signal Process. 42(3): 273-284 (2006) - 2005
- [j2]Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés:
FPGA Implementation of a Pipelined On-Line Backpropagation. J. VLSI Signal Process. 40(2): 189-213 (2005) - 2004
- [j1]Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró:
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocess. Microsystems 28(9): 509-518 (2004)
Conference and Workshop Papers
- 2013
- [c15]Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés:
Experimental Platform for Accelerate the Training of ANNs with Genetic Algorithm and Embedded System on FPGA. IWINAC (2) 2013: 413-420 - 2009
- [c14]Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés, Amaury Lendasse:
RCGA-S/RCGA-SP Methods to Minimize the Delta Test for Regression Tasks. IWANN (1) 2009: 359-366 - [c13]Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch:
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA. ICSAMOS 2009: 1-8 - 2008
- [c12]Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastiá, Fernando Mateo:
SoC-Based Implementation of the Backpropagation Algorithm for MLP. HIS 2008: 744-749 - 2007
- [c11]Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés:
Incidence Position Estimation in a PET Detector Using a Discretized Positioning Circuit and Neural Networks. IWANN 2007: 684-691 - 2005
- [c10]Joaquín Cerdá, Rafael Gadea Gironés, Jorge Daniel Martínez, Angel Sebastiá:
A Tool for Implementing and Exploring SBM Models: Universal 1D Invertible Cellular Automata. IWINAC (1) 2005: 279-289 - 2004
- [c9]Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer:
FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958 - [c8]Joaquín Cerdá-Boluda, Oscar Amoraga-Lechiguero, Ruben Torres-Curado, Rafael Gadea Gironés, Angel Sebastià-Cortés:
FPGA Implementations of the RNR Cellular Automata to Model Electrostatic Field. VECPAR 2004: 382-395 - 2003
- [c7]Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá:
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA. FPL 2003: 776-785 - [c6]Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero:
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression. FPL 2003: 1016-1019 - [c5]Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá:
Implementing a Margolus Neighborhood Cellular Automata on a FPGA. IWANN (2) 2003: 121-128 - 2000
- [c4]Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá, Antonio Mocholí Salcedo:
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks. FPL 2000: 785-788 - [c3]Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo:
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS 2000: 225-230 - 1999
- [c2]Rafael Gadea Gironés, Antonio Mocholí Salcedo:
Implementation with FPGAs of a pipelined on-line backpropagation. ICECS 1999: 1021-1024 - [c1]Rafael Gadea Gironés, Antonio Mocholí Salcedo:
Forward-Backward Parallelism in On-Line Backpropagation. IWANN (2) 1999: 157-165
Reference Works
- 2009
- [r1]Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés:
A 2D Positioning Application in PET Using ANNs. Encyclopedia of Artificial Intelligence 2009: 1576-1582
Coauthor Index
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