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ORCIDAngel Fernandez Herrero
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2010 – 2019
- 2012
[j5]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
:
A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Signal Process. 2012: 218 (2012)- [j4]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras:
Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. J. Circuits Syst. Comput. 21(7) (2012) - 2010
- [j3]Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero:
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010) - [j2]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras:
Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electron. 56(2): 415-422 (2010) - [c6]Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras:
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO 2010: 522-526 - [c5]Gabriel Caffarena, Angel Fernandez Herrero, Juan A. López, Carlos Carreras:
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) 2010: 182-205 - [c4]Gabriel Caffarena, Carlos Carreras, Juan A. López, Angel Fernandez Herrero:
Fast fixed-point optimization of DSP algorithms. VLSI-SoC 2010: 195-200
2000 – 2009
- 2008
- [j1]Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Francisco Javier Casajús-Quirós:
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver. VLSI Design 2008: 312614:1-312614:8 (2008) - [c3]Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo:
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. e-Learning 2008: 161-165 - 2006
- [c2]Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena, Javier Casajús-Quirós:
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. FPL 2006: 1-4 - [c1]Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Javier Casajús-Quirós:
Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver. ICECS 2006: 974-977
Coauthor Index
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