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ORCIDAlberto Jimenez-Pacheco
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2010 – 2019
- 2012
[c6]Alberto Jimenez-Pacheco, Denia Bouhired, Yannick Gasser, Jean-Christophe Zufferey, Dario Floreano, Bixio Rimoldi:
Implementation of a wireless mesh network of ultra light MAVs with dynamic routing. GLOBECOM Workshops 2012: 1591-1596- 2011
- [c5]Alberto Jimenez-Pacheco, Onkar Dabeer:
A novel conflict-free memory and processor architecture for DVB-T2 LDPC decoding. ICUMT 2011: 1-7
2000 – 2009
- 2008
- [j1]Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Francisco Javier Casajús-Quirós:
Design and Implementation of a Hardware Module for MIMO Decoding in a 4G Wireless Receiver. VLSI Design 2008: 312614:1-312614:8 (2008) - 2007
- [c4]Alberto Jimenez-Pacheco:
Turbo Multiuser Detection for MC-CDMA Downlink Systems with Transmit Diversity. VTC Spring 2007: 2666-2671 - 2006
- [c3]Angel Fernandez Herrero, Alberto Jimenez-Pacheco, Gabriel Caffarena
, Javier Casajús-Quirós:
Design and Implementation of a Hardware Module for Equalisation in A 4G MIMO Receiver. FPL 2006: 1-4 - [c2]Alberto Jimenez-Pacheco, Angel Fernandez Herrero, Javier Casajús-Quirós:
Design and Implementation in FPGA of a MIMO Decoder for a 4G Wireless Receiver. ICECS 2006: 974-977 - 2005
- [c1]Alberto Jimenez-Pacheco, Mariano García Otero:
Low complexity iterative receivers for space-time block coded MC-CDMA downlink systems. EUSIPCO 2005: 1-4
Coauthor Index
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