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ORCIDGordon B. Steven
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2000 – 2009
- 2003
[j14]Colin Egan, Gordon B. Steven, Patrick Quick, Rubén Anguera, Fleur L. Steven, Lucian N. Vintan:
Two-level branch prediction using neural networks. J. Syst. Archit. 49(12-15): 557-570 (2003)- 2002
- [c10]Colin Egan, Gordon B. Steven, Lucian N. Vintan:
Cached Two-Level Adaptive Branch Predictors with Multiple Stages. ARCS 2002: 179-194 - 2001
- [j13]Fleur L. Steven, Colin Egan, Richard D. Potter, Gordon B. Steven:
Adding static data dependence collapsing to a high-performance instruction scheduler. J. Syst. Archit. 47(8): 727-745 (2001) - [c9]Gordon B. Steven, Rubén Anguera, Colin Egan, Fleur L. Steven, Lucian N. Vintan:
Dynamic Branch Prediction Using Neural Networks. DSD 2001: 178-185 - [c8]Colin Egan, Gordon B. Steven, Won Shim, Lucian N. Vintan:
Applying Caching to Two-Level Adaptive Branch Prediction. DSD 2001: 186-193 - 2000
- [c7]Daniel Tate, Gordon B. Steven, Fleur L. Steven:
Static Scheduling for Out-of-order Instruction Issue Processors. ACAC 2000: 90-96
1990 – 1999
- 1999
- [c6]Lucian N. Vintan, Cristian Armat, Gordon B. Steven:
The impact of cache organisation on the instruction issue rate of a superscalar processor. PDP 1999: 58-65 - 1998
- [c5]Daniel Tate, Gordon B. Steven, Paul A. Findlay:
The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture. EUROMICRO 1998: 10325-10328 - 1997
- [j12]Gordon B. Steven, Bruce Christianson
, Roger Collins, Richard D. Potter, Fleur L. Steven:
A superscalar architecture to exploit instruction level parallelism. Microprocess. Microsystems 20(7): 391-400 (1997) - 1996
- [c4]Roger Collins, Gordon B. Steven:
Instruction Scheduling for a Superscalar Architecture. EUROMICRO 1996: 643-650 - [c3]Richard D. Potter, Gordon B. Steven:
Investigating the Limits of Fine-Grained Parallelism in a Statically Scheduled Superscalar Architecture. Euro-Par, Vol. II 1996: 779-788 - 1995
- [c2]C. J. Elston, D. B. Christianson, Paul A. Findlay, Gordon B. Steven:
Hades-towards the design of an asynchronous superscalar processor. ASYNC 1995: 200-209 - 1994
- [j11]Roger Collins, Gordon B. Steven:
An explicitly declared delayed-branch mechanism for a superscalar architecture. Microprocess. Microprogramming 40(10-12): 677-680 (1994) - [c1]Rod Adams, Sue M. Gray, Gordon B. Steven:
Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler. PDP 1994: 76-81 - 1993
- [j10]Gordon B. Steven, Fleur L. Steven:
ALU design and processor branch architecture. Microprocess. Microprogramming 36(5): 259-278 (1993) - [j9]Fleur L. Steven, Rod Adams, Gordon B. Steven, L. Wang, D. J. Whale:
Addressing mechanisms for VLIW and superscalar processors. Microprocess. Microprogramming 39(2-5): 75-78 (1993) - [j8]Sue M. Gray, Rod Adams, G. J. Green, Gordon B. Steven:
Static instruction scheduling for the HARP multiple-instruction-issue architecture. Microprocess. Microsystems 17(7): 415-424 (1993) - 1991
- [j7]Rod Adams, Gordon B. Steven:
A parallel pipelined processor with conditional instruction execution. SIGARCH Comput. Archit. News 19(1): 135-142 (1991) - 1990
- [j6]R. G. Adams, Sue M. Gray, Gordon B. Steven:
Utilising low level parallelism in general purpose code: the HARP project. Microprocessing and Microprogramming 29(3): 137-149 (1990) - [j5]Fleur L. Williams, Gordon B. Steven:
How useful are complex instructions? A case study using the M68000. Microprocessing and Microprogramming 29(4): 247-259 (1990) - [j4]Fleur L. Williams, Gordon B. Steven:
Address and data register separation on the M68000 family. SIGARCH Comput. Archit. News 18(2): 85-89 (1990)
1980 – 1989
- 1989
- [j3]Gordon B. Steven, Sue M. Gray, R. G. Adams:
HARP: A parallel pipelined RISC processor. Microprocess. Microsystems 13(9): 579-587 (1989) - 1988
- [j2]Gordon B. Steven, Fleur L. Williams:
General addressing mechanisms for microprocessors. Microprocess. Microsystems 12(2): 67-75 (1988) - [j1]Gordon B. Steven:
A novel effective address calculation mechanism for RISC microprocessors. SIGARCH Comput. Archit. News 16(4): 150-156 (1988)
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