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ORCIDMicroprocessing and Microprogramming, Volume 36
Volume 36, Number 1, November 1992
- Ghulam M. Chaudhry:
On the bandwidth of asynchronous multiprocessors. 1-7 - Martin S. Gilbert, Ramalingam Sridhar:
AMEC - Asynchronous microprogram execution controller. 9-25 - Behrooz Parhami:
Architectural tradeoffs in the design of VLSI-based associative memories. 27-41 - T. P. Troup, T. Donnelly, D. J. Mapps:
Adaptive data interleaving using a microprocessor controlled reconfigurable gate array. 43-48
Volume 36, Number 2, March 1993
- Bandana Majumdar, N. Sankarayya, Arun K. Majumdar:
An ASIC design for edge detection in real time. 55-69 - Stavros D. Nikolopoulos, Roderick MacLeod:
An experimental analysis of event set algorithms for discrete event simulation. 71-81 - S. Selvakumar, C. Siva Ram Murthy:
An efficient heuristic algorithm for mapping parallel programs onto multicomputers. 83-92 - C. Siva Ram Murthy, K. N. Balasubramanya Murthy, A. Sreenivas:
Scheduling of precedence-constrained parallel program tasks on multiprocessors. 93-104
Volume 36, Number 3, May 1993
- Khoa D. Huynh, Taghi M. Khoshgoftaar, Gerald Marazas:
A high-level performance analysis of the IBM subsystem control block (SCB) architecture. 109-125 - Fivos Panetsos
, J. Alonso, E. Barja, Pedro Isasi, V. Olmedo:
NSL: A language for neural network simulation. 127-139 - Anton M. van Wezenbeek, Willem Jan Withagen:
A survey of memory management. 141-162
Volume 36, Number 4, September 1993
- Mohammed Atiquzzaman:
Performance modeling of multiprocessor systems for different data loading schemes. 167-178 - Jaecheol Gong, Byeong Man Kim, Hyunsoo Yoon, Heungkyu Lee, Si-Yeong Hwang:
An improved algorithm for protocol validation by extended circular exploration. 179-194 - George Hassapis:
High level Petri net modelling and analysis of VME-based multiprocessors. 195-204 - Yen-Jen Oyang:
Exploiting multi-way branches to boost superscalar processor performance. 205-213 - Ruslan Raytchev:
Global representation of local time measurements in transputer networks. 215-222
Volume 36, Number 5, October 1993
- Alessandro De Gloria, Paolo Faraboschi, Mauro Olivieri:
Delay insensitive micro-pipelined combinational logic. 225-241 - Antonio González:
A survey of branch techniques in pipelined processors. 243-257 - Gordon B. Steven, Fleur L. Steven:
ALU design and processor branch architecture. 259-278
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