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ORCIDSIGARCH Computer Architecture News, Volume 18
Volume 18, Number 1, March 1990
- V. Dvorak:
Microseqencer architecture supporting arbitrary branching up to 2m targets. 9 - Jack J. Dongarra:
Performance of various computers using standard linear equations software. 17 - Tsong-Chih Hsu, Ling-Yang Kung:
A comment on "a fetch - and - op implementation for parallel computers". 32 - Robert Cousins:
A novel approach to character interfaces. 35 - Robert Cousins:
A reentrant peripheral interface. 43 - Noel W. Anderson:
Amorphous computer system architecture: a preliminary look. 51 - Yen-Jen Oyang, Bor-Ting Chang, Shu-May Lin:
A cost-effective approach to implement a long instruction word microprrocessor. 59 - Carlos Fritsch, Teresa Sánchez, José Javier Anaya:
Primitive based architectures. 73 - Harold Lorin:
A model for recentralization of computing: (distributed processing comes home). 81 - Dan Teodosiu:
Computing in three dimensions. 99 - Gary Frazier:
Ariel: a scalable multiprocessor for the simulation of neural networks. 107 - Robert P. Colwell:
Book review: High-Level Language Computer Architecture edited by Veljko Milutinovic (Computer Science Press, 1989). 120-122 - Behrooz Parhami:
Book review: Advanced Research in VLSI, edited by Charles L. Seitz (The MIT Press, Cambridge, MA, 1989, 373 pp.). 122-123
Volume 18, Number 2, June 1990
- Wolfgang Matthes:
Hardware Resources: a generalizing view on computer architectures. 7-14 - Lawrence Rauchwerger, P. Michael Farmwald:
A multiple floating point coprocessor architecture. 15-24 - Andy Glew, Wen-Mei Hwu:
Snoopy cache test-and-test-and-set without execessive bus contention. 25-32 - Lee Higbee:
Quick and easy cache performance analysis. 33-44 - Arvin Park, Jeffrey C. Becker, Richard J. Lipton:
IOStone: a synthetic file system benchmark. 45-52 - Dionisios N. Pnevmatikatos
, Mark D. Hill:
Cache performance of the integer SPEC benchmarks on a RISC. 53-68 - Anthonie B. Ruighaver:
A modular network for dense optical interconnection of processing elements. 69-75 - Alessandro De Gloria:
VISA: A variable instruction set architecture. 76-84 - Fleur L. Williams, Gordon B. Steven:
Address and data register separation on the M68000 family. 85-89
Volume 18, Number 3a, June 1990
- Jean-Loup Baer, Larry Snyder, James R. Goodman:
Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990. ACM 1990, ISBN 0-89791-366-3 [contents]
Volume 18, Number 3b, September 1990
- Ahmed H. Sameh, Henk A. van der Vorst:
Proceedings of the 4th international conference on Supercomputing, ICS 1990, Amsterdam, The Netherlands, June 11-15, 1990. ACM 1990, ISBN 0-89791-369-8 [contents]
Volume 18, Number 4, December 1990
- Burton Smith:
The end of architecture. 10-17 - Mark D. Hill:
What is scalability? 18-21 - Phillip A. Laplante:
A novel single instruction computer architecture. 22-26 - Ran Ginosar, Nick Michell:
On the potential of asynchronous pipelined processors. 27-34 - Yen-Jen Oyang, Chun-Hung Wen, Yu-Fen Chen, Shu-May Lin:
The effect of employing advanced branching mechanisms in superscalar processors. 35-52 - Yannick Deville:
A low-cost usage-based replacement algorithm for cache memories. 52-58 - Bernard K. Gunther:
A high speed mechanism for short branches. 59-61 - Robert McLaughlin:
Design for fast DSP machine. 62-66 - Werner B. Joerg:
A subclass of Petri Nets as design abstraction for parallel architectures. 67-77 - Mark Thorson:
Usenet Nuggets. 80-89 - Glen G. Langdon Jr.:
Book review: Highly Parallel Computing by George Almasi and Allan Gotlieb (Benjamin/Cummings, 1989). 90 - Glen G. Langdon Jr.:
Book review: Solving Problems on Concurrent Processors, Vol II: Software for Concurrent Processors by I. Angus, G. Fox, J. Kim, and D. Walker (Prentice-Hall, 1990). 90-91 - Marc Dikotter:
Book review: The Definition of Standard ML by R. Milner, M. Torte, R. Harper. 91
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