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ORCIDSIGARCH Computer Architecture News, Volume 16
Volume 16, Number 1, March 1988
- T. Clif Penn:
Preface to the Special issue on Neural Networks. 6 - Richard P. Lippmann:
An introduction to computing with neural nets. 7-25 - James A. Anderson, Edward J. Wisniewski, Susan R. Viscuso:
Software for neural networks. 26-36 - Simon Garth, Danny Pike:
An integrated system for neural network simulations. 37-44 - A. Jean Maren:
Conference report: IEEE 1'st Int'l conference on neural networks. 45-46 - Jack J. Dongarra:
Performance of various computers using standard linear equations software in a FORTRAN environment. 47-69 - William A. Wulf:
The WM computer architecture. 70-84 - Daniel Tabak:
Logarithmic indices for multiprocessor evaluation. 85-90 - Martin Dowd:
An example RISC vector machine architecture. 91-99 - Martin Dowd:
RISC vector CPU's and crossbars in desktops. 100-102 - Stanley E. Lass:
Multiple instructions/operands per access to cache memory. 103 - Wanda Gass:
Workshop report: synthesis of foo bars. 104-108 - F. Joel Ferguson:
Book Review: Logic Design Principles by Edward J. McCluskey: Prentice-Hall Publishers, Englewood Cliffs, New Jersey, 549 pp., $39.95. 109
Volume 16, Number 2, May 1988
- Howard Jay Siegel:
Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988. IEEE Computer Society 1988, ISBN 0-8186-0861-7 [contents]
Volume 16, Number 3, June 1988
- David R. Cheriton, Patrick D. Boyle, Gert Slavenburg:
Comments on "'Coherency for multiprocessor virtual addresses caches' by James R. Goodman". 3-6 - James R. Goodman:
Reply to David R. Cheriton's, Pat Boyle's, and Gert A. Slavenburg's "Comments on 'Coherency for multiprocessor virtual addressed caches' by James R. Goodman". 7 - Guy Rabbat, Borko Furht, Ron Kibler:
Three-dimensional computers and measuring their performance. 9-16 - Michel Castan, Alessandro Contessa, Eric Cousin, Christophe Coustet, Bernard Lécussan:
MaRs: a parallel graph reduction multiprocessor. 17-24 - Alessandro Contessa:
An approach to fault tolerance and error recovery in a parallel graph reduction machine: MaRS - a case study. 25-32 - Chuck Crawford:
Evolution of the Harris H-series computers and speculations on their future. 33-39 - Philip l. Good:
Structuring an instruction cache. 40-43 - Eric E. Johnson:
Completing an MIMD multiprocessor taxonomy. 44-47 - Douglas W. Jones:
The ultimate RISC. 48-55 - Douglas W. Jones:
A minimal CISC. 56-63 - Stanley E. Lass:
Shared cache multiprocessing with pack computers. 64-70 - Norman P. Jouppi:
Superscalar vs. superpipelined machines. 71-80 - Lorne H. Schachter:
Book review of "High-performance computer architecture by Harold S. Stone. Addison-Wesley 1987. 81-84
Volume 16, Number 4, September 1988
- Umakishore Ramachandran:
Preface to the Special Issue on Architectural Support for Operating Systems. 11 - Abhaya Asthana, H. V. Jagadish, J. A. Chandross, D. Lin, Scott C. Knauer:
An intelligent memory system. 12-20 - Monica Beltrametti, Kenneth Bobey, John R. Zorbas:
The control mechanism for the Myrias parallel computer system. 21-30 - Raphael A. Finkel, Debra Hensgen:
YACKOS on a shared-memory multiprocessor. 31-36 - Marc F. Pucci, James L. Alberi:
Optimized communication in an extended remote procedure call model. 37-46 - Jordi Cortadella
, Teodor Jové:
Dynamic RAM for on-chip instruction caches. 45-50 - Mahsoo Naderi:
Modelling and performance evaluation of multiprocessors organization with shared memories. 51-74 - Edward F. Gehringer, Janne Abullarade, Michael H. Gulyn:
A survey of commercial parallel processors. 75-107 - Mark Lease, Mac Lively:
Comparing production system architectures. 108-116 - Ivor P. Page, Jeff Niehaus:
The Flex architecture, a high speed graphics processor. 117-129 - Kazuaki J. Murakami, Akira Fukuda, Toshinori Sueyoshi, Shinji Tomita:
An overview of the Kyushu University reconfigurable parallel processor. 130-137 - Ora E. Percus, Jerome K. Percus:
Some results concerning clock-regulated queues. 138-144 - Fleur Liane Williams:
Should SCC set condition codes? 145-149 - Gordon B. Steven:
A novel effective address calculation mechanism for RISC microprocessors. 150-156 - Behrooz Parhami:
From defects to failures: a view of dependable computing. 157-168 - David A. Patterson:
RISCY patents. 169-191 - Helen C. Takacs:
Book review: A VLSI Architecture for Concurrent Data Structures by William J. Dally (Kluwer 1988). 192-193 - Robert P. Colwell:
Book review: Computer Architecture and Organization, 2nd ed. by John P. Hayes (McGraw Hill, 1988). 193-195 - Charles E. McDowell:
Book review: Supercomputer Architectures by Paul B. Schneck (Kluwer Academic Publishers). 195-196
Volume 16, Number 5, December 1988
- Herbert H. J. Hum, Guang R. Gao:
Summary of the workshop on frontiers in functional programming and dataflow architecture. 12-19 - André M. Van Tilborg:
Instrumentation for distributed computing systems. 20-25 - Glenn W. Griffin:
The ultimate ultimate RISC. 26-32 - Douglas W. Jones:
Risks of comparing RISCs. 33-34 - Mahsoo Naderi:
Modelling and performance evaluation of multiprocessors, organizations with multi-memory units. 35-51 - Peter M. Kogge, John V. Oldfield, Mark R. Brule, Charles D. Stormon:
VLSI and rule-based systems. 52-65 - Behrooz Parhami:
Book review: Memory Storage Patterns in Parallel Processing by Mary A. Mace (Kluwer Academic Publishers, Boston, 1987, 139 pp.). 76
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