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Journal Articles
- 2014
[j2]Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang:
A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3416-3425 (2014)- 2010
- [j1]Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu:
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1843-1847 (2010)
Conference and Workshop Papers
- 2014
- [c4]Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. SoCC 2014: 455-462 - 2013
- [c3]Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih:
A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS 2013: 1468-1471 - [c2]Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu:
A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC 2013: 110-115 - 2009
- [c1]Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li:
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. VTS 2009: 15-20
Coauthor Index
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