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2020 – today
- 2022
[c19]Yu-Jen Huang, Guan-Ting Lin, Pin-Hsuan Ting, Zheng-Wei Huang, Shao-Hung Yu, Yi-Jun Cai, Chia-Chien Wei, Sien Chi, Chun-Ting Lin:
Mobile 14-GHz Bandwidth Fronthaul Link Supporting 128 RF-Chain Signals for 6G Ma-MIMO Beamforming. OFC 2022: 1-3- [c18]Chia-Chien Wei, Yu-Jen Huang, Zhen-Xiong Xie, Ping-Yao Huang, Pin-Hsuan Ting, Chun-Ting Lin:
>100 Gbps 3×3 MIMO V-Band RoF System for up to 100 m Wireless Transmission Enabled by NN-based Equalization. OFC 2022: 1-3 - 2021
- [c17]Liang-Wei Tao, An-Fong Hwu, Yu-Jen Huang, Chi-Chung Chen, Chao-Yuan Yeh, Shih-Hao Hung:
End-to-End Performance Optimization for Training Streaming Convolutional Neural Networks using Billion-Pixel Whole-Slide Images. IEEE BigData 2021: 1127-1137 - 2020
- [c16]Yu-Jen Huang, Ko-Wei Huang, Shih-Hsiung Lee
:
Defect Detection of Stainless Steel Plates Using Deep Learning Technology. ICPR Workshops (4) 2020: 289-301
2010 – 2019
- 2014
- [j12]Yu-Jen Huang, Jin-Fu Li:
Yield-enhancement schemes for multicore processor and memory stacked 3D ICs. ACM Trans. Embed. Comput. Syst. 13(3s): 106:1-106:22 (2014) - [c15]Chung-Ming Huang, Yuan-Tse Yu, Yu-Jen Huang:
A Cross-layer Loss Discrimination Scheme for DCCP over the Wireless Network. ANT/SEIT 2014: 77-84 - 2013
- [j11]Chun-Kai Lai, Yu-Jen Huang, Jin-Fu Li:
A Self-Repair Technique for Content Addressable Memories with Address-Input-Free Writing Function. J. Inf. Sci. Eng. 29(3): 493-507 (2013) - [j10]Che-Wei Chou, Yu-Jen Huang, Jin-Fu Li:
A Built-In Self-Repair Scheme for 3-D RAMs With Interdie Redundancy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 572-583 (2013) - [c14]Yu-Jen Huang, Mark T. Bolas, Evan A. Suma:
Fusing depth, color, and skeleton data for enhanced real-time hand segmentation. SUI 2013: 85 - 2012
- [j9]Yu-Jen Huang, Jin-Fu Li:
Built-In Self-Repair Scheme for the TSVs in 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(10): 1600-1613 (2012) - [j8]Shun-Hsun Yang, Yu-Jen Huang, Jin-Fu Li:
A Low-Power Ternary Content Addressable Memory With Pai-Sigma Matchlines. IEEE Trans. Very Large Scale Integr. Syst. 20(10): 1909-1913 (2012) - [j7]Yu-Jen Huang, Jin-Fu Li:
Low-Cost Self-Test Techniques for Small RAMs in SOCs Using Enhanced IEEE 1500 Test Wrappers. IEEE Trans. Very Large Scale Integr. Syst. 20(11): 2123-2127 (2012) - [c13]Li-Jung Chang, Yu-Jen Huang, Jin-Fu Li:
Area and reliability efficient ECC scheme for 3D RAMs. VLSI-DAT 2012: 1-4 - [c12]Yu-Jen Huang, Jin-Fu Li, Che-Wei Chou:
Post-bond test techniques for TSVs with crosstalk faults in 3D ICs. VLSI-DAT 2012: 1-4 - [c11]Yong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li:
Test cost optimization technique for the pre-bond test of 3D ICs. VTS 2012: 102-107 - 2011
- [c10]Yu-Jen Huang, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs. VTS 2011: 20-25 - 2010
- [j6]Tsu-Wei Tseng, Yu-Jen Huang, Jin-Fu Li:
DABISR: A Defect-Aware Built-In Self-Repair Scheme for Single/Multi-Port RAMs in SoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1628-1639 (2010) - [j5]Jin-Fu Li, Yu-Jen Huang, Yong-Jyun Hu:
Testing Random Defect and Process Variation Induced Comparison Faults of TCAMs With Asymmetric Cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1843-1847 (2010) - [c9]Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li:
A low-cost built-in self-test scheme for an array of memories. ETS 2010: 75-80 - [c8]Yu-Jen Huang, Yun-Chao You, Jin-Fu Li:
Enhanced IEEE 1500 test wrapper for testing small RAMs in SOCs. SoCC 2010: 236-240
2000 – 2009
- 2009
- [j4]Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li:
Memory Built-in Self Test in Multicore Chips with Mesh-Based Networks. IEEE Micro 29(5): 46-55 (2009) - [c7]Yu-Jen Huang, Jin-Fu Li:
Testability Exploration of 3-D RAMs and CAMs. Asian Test Symposium 2009: 397-402 - [c6]Yong-Jyun Hu, Yu-Jen Huang, Jin-Fu Li:
Modeling and Testing Comparison Faults of TCAMs with Asymmetric Cells. VTS 2009: 15-20 - 2008
- [j3]Da-Ming Chang, Jin-Fu Li, Yu-Jen Huang:
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. J. Electron. Test. 24(1-3): 181-192 (2008) - [c5]Yu-Jen Huang, Jin-Fu Li:
A Low-Cost Pipelined BIST Scheme for Homogeneous RAMs in Multicore Chips. ATS 2008: 357-362 - 2007
- [j2]Yu-Jen Huang, Jin-Fu Li:
Testing ternary content addressable memories with active neighbourhood pattern-sensitive faults. IET Comput. Digit. Tech. 1(3): 246-255 (2007) - [j1]Lai-Jiu Lin, Qamrul Hasan Ansari, Yu-Jen Huang:
Some existence results for solutions of generalized vector quasi-equilibrium problems. Math. Methods Oper. Res. 65(1): 85-98 (2007) - [c4]Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li, Alex Pao, Kevin Chiu, Eliot Chen:
A Built-In Self-Repair Scheme for Multiport RAMs. VTS 2007: 355-360 - 2006
- [c3]Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li:
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. DFT 2006: 362-370 - [c2]Yu-Jen Huang, Jin-Fu Li:
Testing Active Neighborhood Pattern-Sensitive Faults of Ternary Content Addressable Memories. ETS 2006: 55-62 - 2005
- [c1]Jin-Fu Li, Jiunn-Der Yu, Yu-Jen Huang:
A design methodology for hybrid carry-lookahead/carry-select adders with reconfigurability. ISCAS (1) 2005: 77-80
Coauthor Index
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