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2000 – 2009
- 2007
[c7]Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407- 2006
- [j2]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - 2004
- [j1]Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
:
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(7): 1020-1030 (2004) - 2002
- [c6]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically constrained logic synthesis. ICCAD 2002: 679-686 - [c5]Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-179 - [c4]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - 2001
- [c3]Subarnarekha Sinha, Andreas Kuehlmann, Robert K. Brayton:
Sequential SPFDs. ICCAD 2001: 84-90 - 2000
- [c2]Subarnarekha Sinha, Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. ICCD 2000: 494-503
1990 – 1999
- 1998
- [c1]Subarnarekha Sinha, Robert K. Brayton:
Implementation and use of SPFDs in optimizing Boolean networks. ICCAD 1998: 103-110
Coauthor Index
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