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Ivan de Paúl
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Journal Articles
- 2008
- [j3]José Luis Rosselló, Ivan de Paúl, Vincent Canals:
Self-configuring spiking neural networks. IEICE Electron. Express 5(22): 921-926 (2008) - [j2]José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro:
A simple CMOS chaotic integrated circuit. IEICE Electron. Express 5(24): 1042-1048 (2008) - 2007
- [j1]Bartomeu Alorda, Ivan de Paúl, Jaume Segura:
Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. 1(5): 481-490 (2007)
Conference and Workshop Papers
- 2023
- [c12]Sebastià A. Bota, Salvador Barceló, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura:
A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS 2023: 1-6 - 2022
- [c11]Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura:
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. IEEE SENSORS 2022: 1-4 - 2018
- [c10]Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd:
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. ISCAS 2018: 1-5 - 2013
- [c9]Sebastià A. Bota, Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, L. A. Segura:
Accurate alpha soft error rate evaluation in SRAM memories. IOLTS 2013: 205-209 - 2009
- [c8]José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro:
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. ICANN (1) 2009: 421-428 - [c7]José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl:
Practical Hardware Implementation of Self-configuring Neural Networks. ISNN (3) 2009: 1154-1159 - 2008
- [c6]José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura:
Using stochastic logic for efficient pattern recognition analysis. IJCNN 2008: 1057-1061 - 2006
- [c5]José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura:
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN 2006: 659-663 - 2004
- [c4]Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura:
A BIST-based Charge Analysis for Embedded Memories. IOLTS 2004: 199-206 - 2002
- [c3]Ivan de Paúl, Miquel Roca, Oscar Calvo, Raul Velazco:
SEU fault injection in simulation environments: example of VHDL configuration on FPGA device. LATW 2002: 114-119 - 2001
- [c2]Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden:
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS 2001: 286-291 - 2000
- [c1]Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller:
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW 2000: 87-91
Informal and Other Publications
- 2024
- [i1]Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastià A. Bota, Jaume Segura:
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR abs/2402.10917 (2024)
Coauthor Index
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