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2020 – today
- 2023
[c8]Selenia María Medina Hernández, Pedro P. Carballo, Pedro Hernández-Fernández, David S. Miranda Guillén, Sergio González:
SoC FPGA-based Multichannel Data Acquisition System with Linux-Baremetal AMP for Applications in the Field of Astrophysics. DCIS 2023: 1-6- [c7]Gabriel Santana Quintana
, Pedro P. Carballo, Carlos Betancor:
Design of SoC FPGA based controller to reduce shadow effects in photovoltaic installations. DCIS 2023: 1-6 - [c6]Mario Guanche-Hernández, Raquel León, Pedro P. Carballo:
MPSoC FPGA Implementation of Algorithms of Machine Learning for Clinical Applications Using High-Level Design Methodology. DSD 2023: 764-769
2010 – 2019
- 2019
- [c5]Raquel León, Adrián Domínguez, Pedro P. Carballo, Antonio Núñez:
Deep Packet Inspection Through Virtual Platforms using System-On-Chip FPGAs. DCIS 2019: 1-6 - 2017
- [c4]Adrián Domínguez, Pedro P. Carballo, Antonio Núñez:
Programmable SoC platform for deep packet inspection using enhanced Boyer-Moore algorithm. ReCoSoC 2017: 1-8 - 2013
- [c3]Pedro P. Carballo, Omar Espino, Romén Neris, Pedro Hernandez-Fernandez, Tomasz Szydzik, Antonio Núñez:
Scalable Video Coding Deblocking Filter FPGA and ASIC Implementation Using High-Level Synthesis Methodology. DSD 2013: 415-422
2000 – 2009
- 2009
- [e1]Antonio Núñez, Pedro P. Carballo:
12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2009, 27-29 August 2009, Patras, Greece. IEEE Computer Society 2009, ISBN 978-0-7695-3782-5 [contents] - 2006
- [c2]Armando Sánchez-Peña, Pedro P. Carballo, Luz García, Antonio Núñez:
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. DSD 2006: 305-312 - 2004
- [c1]Víctor Reyes, Tomás Bautista, Gustavo Marrero Callicó, Pedro P. Carballo, Wido Kruijtzer:
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-Chip. DSD 2004: 476-483
1990 – 1999
- 1993
- [j3]Pedro P. Carballo, Roberto Sarmiento, Antonio Núñez:
Integer and control units for a GaAs 32-bit RISC processor. Microprocess. Microprogramming 37(1-5): 105-108 (1993) - 1991
- [j2]K. Eshraghian, Roberto Sarmiento, Pedro P. Carballo, Antonio Núñez:
Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation. Microprocessing and Microprogramming 32(1-5): 75-82 (1991)
1980 – 1989
- 1989
- [j1]Antonio Núñez, Roberto Sarmiento, Pedro P. Carballo:
Some results in GaAs processor design using LSI integrated circuits. Microprocess. Microprogramming 25(1-5): 127-132 (1989)
Coauthor Index
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