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ORCIDRoy E. Scheuerlein
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Journal Articles
- 1992
[j5]Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong:
A pulsed sensing scheme with a limited bit-line swing. IEEE J. Solid State Circuits 27(4): 678-682 (1992)- [j4]Robert L. Franch, Sang H. Dhong, Roy E. Scheuerlein:
A large V/sub DS/ data retention test pattern for DRAM's. IEEE J. Solid State Circuits 27(8): 1214-1217 (1992) - [j3]Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa:
A 14-ns 14-Mb CMOS DRAM with 300-mW active power. IEEE J. Solid State Circuits 27(9): 1222-1228 (1992) - 1989
- [j2]Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano:
A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing. IEEE J. Solid State Circuits 24(5): 1198-1205 (1989) - 1988
- [j1]Roy E. Scheuerlein, James D. Meindl:
Offset word-line architecture for scaling DRAMs to the gigabit level. IEEE J. Solid State Circuits 23(1): 41-47 (1988)
Coauthor Index
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