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Books and Theses
- 2007
[b1]Kiyoo Itoh, Masashi Horiguchi, Hitoshi Tanaka:
Ultra-Low Voltage Nano-Scale Memories. Series on Integrated Circuits and Systems, Springer 2007, ISBN 978-0-387-33398-4, pp. 1-346
Journal Articles
- 2021
- [j15]Cheng Yin
, Le Thanh Binh, Duong Tran Anh, Son T. Mai, Anh Le, Van-Hau Nguyen, Van-Chien Nguyen, Nguyen Xuan Tinh, Hitoshi Tanaka, Nguyen Trung Viet, Long Dinh Nguyen, Trung Q. Duong:
Advanced Machine Learning Techniques for Predicting Nha Trang Shorelines. IEEE Access 9: 98132-98149 (2021) - [j14]Vahid Nourani, Hessam Najafi, Alireza Babaeian Amini, Hitoshi Tanaka:
Using Hybrid Wavelet-Exponential Smoothing Approach for Streamflow Modeling. Complex. 2021: 6611848:1-6611848:17 (2021) - 2015
- [j13]Hirotake Kajii, Masato Ise, Hitoshi Tanaka, Takahiro Ohtomo, Yutaka Ohmori:
Influence of Polymer Gate Dielectrics on p-Channel and n-Channel Formation of Fluorene-type Polymer Light-emitting Transistors. IEICE Trans. Electron. 98-C(2): 139-142 (2015) - [j12]Sadek Gala, Yoshihiro Sawano, Hitoshi Tanaka:
A remark on two generalized Orlicz-Morrey spaces. J. Approx. Theory 198: 1-9 (2015) - 2007
- [j11]Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme. IEEE J. Solid State Circuits 42(1): 201-209 (2007) - 2005
- [j10]Kouji Tsunoda, Akira Sato, Hiroko Tashiro, Toshiro Nakanishi, Hitoshi Tanaka:
Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications. IEICE Trans. Electron. 88-C(4): 608-613 (2005) - 2003
- [j9]Hitoshi Tanaka, Yutaka Fujita, Hiroto Yamaji:
Visualization of large-scale internal seiche in Lake Inawashiro. J. Vis. 6(1): 4 (2003) - [j8]Hitoshi Tanaka, Jingtao Huang, Masafumi Hagiwara:
A concepts-of-sentences associative neural network. Syst. Comput. Jpn. 34(11): 43-54 (2003) - 1999
- [j7]Hitoshi Tanaka, Masakazu Aoki, Takeshi Sakata, Shin'ichiro Kimura, Narumi Sakashita, Hideto Hidaka, Tadashi Tachibana, Katsutaka Kimura:
A precise on-chip voltage generator for a gigascale DRAM with a negative word-line scheme. IEEE J. Solid State Circuits 34(8): 1084-1090 (1999) - 1997
- [j6]Takao Watanabe, Ryo Fujita, Kazumasa Yanagisawa, Hitoshi Tanaka, Kazushige Ayukawa, Mitsuru Soga, Yuji Tanaka, Yoshimitsu Sugie, Yoshinobu Nakagome:
A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. IEEE J. Solid State Circuits 32(5): 635-641 (1997) - 1995
- [j5]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - 1994
- [j4]Hitoshi Tanaka, Yoshinobu Nakagome, Jun Etoh, Eiji Yamasaki, Masakazu Aoki, Kazuyuki Miyazawa:
Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid State Circuits 29(4): 448-453 (1994) - 1991
- [j3]Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh:
An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid State Circuits 26(4): 465-472 (1991) - [j2]Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki:
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. IEEE J. Solid State Circuits 26(7): 1003-1010 (1991) - 1990
- [j1]Masashi Horiguchi, Masakazu Aoki, Jun Etoh, Hitoshi Tanaka, Shin'ichi Ikenaga, Kiyoo Itoh, Kazuhiko Kajigaya, Hiroaki Kotani, Kazuyoshi Ohshima, Tetsuro Matsumoto:
A tunable CMOS-DRAM voltage limiter with stabilized feedback amplifier. IEEE J. Solid State Circuits 25(5): 1129-1135 (1990)
Conference and Workshop Papers
- 2024
- [c3]Shunnosuke Sonobe, Hitoshi Tanaka, Akio Fujiyoshi:
Automatic Generation of Tactile Graphics of Characters to Support Handwriting of Blind Individuals. ICCHP (1) 2024: 260-266 - 2011
- [c2]Keisuke Suzuki, Hitoshi Tanaka, Yoshiki Miichi, Masami Aga:
Estimating damage-mitigation level of collision-prevention support braking. Intelligent Vehicles Symposium 2011: 648-653 - 2006
- [c1]Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. ISSCC 2006: 557-566
Informal and Other Publications
- 2022
- [i1]Yuzhu Li, Tairan Liu, Hatice Ceylan Koydemir, Hongda Wang, Keelan O'Riordan, Bijie Bai, Yuta Haga, Junji Kobashi, Hitoshi Tanaka, Takaya Tamaru, Kazunori Yamaguchi, Aydogan Ozcan:
Deep Learning-enabled Detection and Classification of Bacterial Colonies using a Thin Film Transistor (TFT) Image Sensor. CoRR abs/2205.03549 (2022)
Coauthor Index
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