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ORCIDKuan-Yu Chen 0001
Person information
- affiliation (PhD 2024): University of Michigan, Department of Electrical Engineering and Computer Science, Ann Arbor, MI, USA
- affiliation: Tenstorrent USA, Inc., Austin, TX, USA
Other persons with the same name
- Kuan-Yu Chen — disambiguation page
- Kuan-Yu Chen 0002
![[0000-0001-9656-7551]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-9656-7551")
— National Taiwan University of Science and Technology, Computer Science and Information Engineering Department, Taipei, Taiwan (and 1 more) - Kuan-Yu Chen 0003 — National Cheng Kung University, Department of Electrical Engineering, Institute of Microelectronics, Tainan, Taiwan (and 1 more)
- Kuan-Yu Chen 0004 — Chaoyang University of Technology, Department of Information and Communication Engineering, Taichung, Taiwan (and 1 more)
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2020 – today
- 2025
[j5]Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. IEEE J. Solid State Circuits 60(2): 672-684 (2025)- 2024
- [j4]Anish Krishnakumar, Hanguang Yu, Tutu Ajayi, A. Alper Goksoy, Vishrut Pandey, Joshua Mack, Md Sahil Hassan, Kuan-Yu Chen, Chaitali Chakrabarti, Daniel W. Bliss, Ali Akoglu, Hun-Seok Kim, Ronald G. Dreslinski, David T. Blaauw, Ümit Y. Ogras:
FALCON: An FPGA Emulation Platform for Domain-Specific SoCs (DSSoCs). IEEE Des. Test 41(1): 70-80 (2024) - [j3]Kuan-Yu Chen, Thomas Mason Nelson, Alireza Khadem, Morteza Fayazi, Sanjay Sri Vallabh Singapuram, Ronald G. Dreslinski, Nishil Talati, Hun-Seok Kim, David T. Blaauw:
Canalis: A Throughput-Optimized Framework for Real-Time Stream Processing of Wireless Communication. ACM Trans. Reconfigurable Technol. Syst. 17(4): 61:1-61:32 (2024) - [c14]Seungkyu Choi, Huanshihong Deng, Kuan-Yu Chen, Yufan Yue, David T. Blaauw, Hun-Seok Kim:
ParaBase: A Configurable Parallel Baseband Processor for Ultra-High-Speed Inter-Satellite Optical Communications. ISLPED 2024: 1-6 - 2023
- [c13]Yufeng Gu, Arun Subramaniyan, Timothy Dunn, Alireza Khadem, Kuan-Yu Chen, Somnath Paul, Md. Vasimuddin, Sanchit Misra, David T. Blaauw, Satish Narayanasamy, Reetuparna Das:
GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. ISCA 2023: 25:1-25:15 - 2022
- [j2]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A 36-Core Systolic Multiprocessor With Dynamically Reconfigurable Interconnect and Memory. IEEE J. Solid State Circuits 57(4): 986-998 (2022) - [c12]Xin He, Kuan-Yu Chen, Siying Feng, Hun-Seok Kim, David T. Blaauw, Ronald G. Dreslinski, Trevor N. Mudge:
Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor. PACT 2022: 148-159 - [c11]Leul Belayneh, Haojie Ye, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski, Nishil Talati:
Locality-Aware Optimizations for Improving Remote Memory Latency in Multi-GPU Systems. PACT 2022: 304-316 - [c10]Nishil Talati, Haojie Ye, Yichen Yang, Leul Belayneh, Kuan-Yu Chen, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski:
NDMiner: accelerating graph pattern mining using near data processing. ISCA 2022: 146-159 - [c9]Siying Feng, Xin He, Kuan-Yu Chen, Liu Ke, Xuan Zhang, David T. Blaauw, Trevor N. Mudge, Ronald G. Dreslinski:
MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows. ISCA 2022: 245-258 - [c8]Daniel W. Bliss, Tutu Ajayi, Ali Akoglu, Ilkin Aliyev, Toygun Basaklar, Leul Belayneh, David T. Blaauw, John S. Brunhaver, Chaitali Chakrabarti, Liangliang Chang, Kuan-Yu Chen, Ming-Hung Chen, Xing Chen, Alex R. Chiriyath, Alhad Daftardar, Ronald G. Dreslinski, Arindam Dutta, Allen-Jasmin Farcas, Y. Fu, A. Alper Goksoy, Xin He, Md Sahil Hassan, Andrew Herschfelt, Jacob Holtom, Hun-Seok Kim, A. N. Krishnakumar, Yang Li, Owen Ma, Joshua Mack, Saurav Mallik, Sumit K. Mandal, Radu Marculescu, Brittany M. McCall, Trevor N. Mudge, Ümit Y. Ogras, Vishrut Pandey, Saquib Ahmad Siddiqui, Yu-Hsiu Sun, Adarsh A. Venkataramani, Xiangdong Wei, B. R. Willis, Hanguang Yu, Yufan Yue:
Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. ISCAS 2022: 443-447 - [c7]Chien-Wei Tseng, Demba Komma, Kuan-Yu Chen, Rohit Rothe, Zhen Feng, Makoto Yasuda, Masaru Kawaminami, Hun-Seok Kim, David T. Blaauw:
A Long-Range Narrowband RF Localization System with a Crystal-Less Frequency-Hopping Receiver. ISSCC 2022: 392-394 - [c6]Nishil Talati, Haojie Ye, Sanketh Vedula, Kuan-Yu Chen, Yuhan Chen, Daniel Liu, Yichao Yuan, David T. Blaauw, Alex M. Bronstein, Trevor N. Mudge, Ronald G. Dreslinski:
Mint: An Accelerator For Mining Temporal Motifs. MICRO 2022: 1270-1287 - [c5]Kuan-Yu Chen, Chi-Sheng Yang, Yu-Hsiu Sun, Chien-Wei Tseng, Morteza Fayazi, Xin He, Siying Feng, Yufan Yue, Trevor N. Mudge, Ronald G. Dreslinski, Hun-Seok Kim, David T. Blaauw:
A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. VLSI Technology and Circuits 2022: 202-203 - 2021
- [c4]Timothy Dunn, Harisankar Sadasivan, Jack Wadden, Kush Goliya, Kuan-Yu Chen, David T. Blaauw, Reetuparna Das, Satish Narayanasamy:
SquiggleFilter: An Accelerator for Portable Virus Detection. MICRO 2021: 535-549 - [c3]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. VLSI Circuits 2021: 1-2 - [i1]Sung Kim, Morteza Fayazi, Alhad Daftardar, Kuan-Yu Chen, Jielun Tan, Subhankar Pal, Tutu Ajayi, Yan Xiong, Trevor N. Mudge, Chaitali Chakrabarti, David T. Blaauw, Ronald G. Dreslinski, Hun-Seok Kim:
Versa: A Dataflow-Centric Multiprocessor with 36 Systolic ARM Cortex-M4F Cores and a Reconfigurable Crossbar-Memory Hierarchy in 28nm. CoRR abs/2109.03024 (2021) - 2020
- [j1]Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. IEEE J. Solid State Circuits 55(4): 933-944 (2020) - [c2]Xin He, Subhankar Pal, Aporva Amarnath, Siying Feng, Dong-Hyeon Park, Austin Rovinski, Haojie Ye, Kuan-Yu Chen, Ronald G. Dreslinski, Trevor N. Mudge:
Sparse-TPU: adapting systolic arrays for sparse matrices. ICS 2020: 19:1-19:12
2010 – 2019
- 2019
- [c1]Subhankar Pal, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits 2019: 150-
Coauthor Index
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