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"A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator ..."
Subhankar Pal et al. (2019)
- Subhankar Pal
, Dong-Hyeon Park, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao
, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen
, Chaitali Chakrabarti, Michael B. Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. VLSI Circuits 2019: 150-
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