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ORCIDJessy Clédière
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2020 – today
- 2024
[c22]Clément Fanjas, Driss Aboulkassimi, Simon Pontié, Jessy Clédière:
PoP DRAM: A new EMFI approach based on EM-induced glitches on SoC. FDTC 2024: 10-21- 2023
- [c21]S. Bouat, Stéphanie Anceau, Laurent Maingault, Jessy Clédière, Luc Salvo, Rémi Tucoulou:
X ray nanoprobe for fault attacks and circuit edits on 28-nm integrated circuits. DFT 2023: 1-6 - [c20]Clément Fanjas, Driss Aboulkassimi, Simon Pontié, Jessy Clédière:
Exploration of System-on-Chip Secure-Boot Vulnerability to Fault-Injection by Side-Channel Analysis. DFT 2023: 1-6 - 2021
- [c19]Laurent Maingault
, Stéphanie Anceau, Manuel Sulmont, Luc Salvo, Jessy Clédière, Pierre Lhuissier, Emrick Beliard, Jean-Luc Rainard:
Laboratory X-rays Operando Single Bit Attacks on Flash Memory Cells. CARDIS 2021: 139-150 - [c18]Thomas Trouchkine, Guillaume Bouffard, Jessy Clédière:
EM Fault Model Characterization on SoCs: From Different Architectures to the Same Fault Model. FDTC 2021: 31-38
2010 – 2019
- 2019
- [c17]Thomas Trouchkine, Guillaume Bouffard, Jessy Clédière:
Fault Injection Characterization on Modern CPUs. WISTP 2019: 123-138 - 2017
- [c16]Stéphanie Anceau, Pierre Bleuet, Jessy Clédière, Laurent Maingault, Jean-Luc Rainard, Rémi Tucoulou:
Nanofocused X-Ray Beam to Reprogram Secure Circuits. CHES 2017: 175-188 - 2015
- [c15]Louis Dureuil, Marie-Laure Potet, Philippe de Choudens, Cécile Dumas, Jessy Clédière:
From Code Review to Fault Injection Attacks: Filling the Gap Using Fault Model Inference. CARDIS 2015: 107-124 - [c14]Loïc Zussa, Ingrid Exurville, Jean-Max Dutertre, Jean-Baptiste Rigaud, Bruno Robisson, Assia Tria, Jessy Clédière:
Evidence of an information leakage between logically independent blocks. CS2@HiPEAC 2015: 25-30 - 2014
- [c13]Loïc Zussa, Amine Dehbaoui, Karim Tobich, Jean-Max Dutertre, Philippe Maurine, Ludovic Guillaume-Sage, Jessy Clédière, Assia Tria:
Efficiency of a glitch detector against electromagnetic fault injection. DATE 2014: 1-6 - [c12]Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson:
Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. HOST 2014: 130-135 - 2013
- [j3]Mathilde Soucarros, Jessy Clédière, Cécile Canovas-Dumas, Philippe Elbaz-Vincent:
Fault Analysis and Evaluation of a True Random Number Generator Embedded in a Processor. J. Electron. Test. 29(3): 367-381 (2013) - [c11]Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Assia Tria:
Power supply glitch induced faults on FPGA: An in-depth analysis of the injection mechanism. IOLTS 2013: 110-115 - 2011
- [j2]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin:
Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA. J. Cryptol. 24(2): 247-268 (2011) - [c10]Mathilde Soucarros, Cécile Canovas-Dumas, Jessy Clédière, Philippe Elbaz-Vincent, Denis Réal:
Influence of the temperature on true random number generators. HOST 2011: 24-27 - 2010
- [c9]Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA. ASAP 2010: 115-122 - [c8]Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin:
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. ETS 2010: 251
2000 – 2009
- 2009
- [c7]Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin:
Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA. VTS 2009: 327-332 - 2008
- [c6]Thanh-Ha Le, Cécile Canovas, Jessy Clédière:
An overview of side channel analysis attacks. AsiaCCS 2008: 33-43 - [c5]Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette:
Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. DATE 2008: 1274-1279 - [c4]Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle:
Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA. IOLTS 2008: 289-294 - 2007
- [j1]Thanh-Ha Le, Jessy Clédière, Christine Servière, Jean-Louis Lacoume:
Noise Reduction in Side Channel Attack Using Fourth-Order Cumulant. IEEE Trans. Inf. Forensics Secur. 2(4): 710-720 (2007) - [c3]Thanh-Ha Le, Jessy Clédière, Christine Servière, Jean-Louis Lacoume:
Efficient Solution for Misalignment of Signal in Side Channel Analysis. ICASSP (2) 2007: 257-260 - [i2]Thanh-Ha Le, Quoc-Thinh Nguyen-Vuong, Cécile Canovas, Jessy Clédière:
Novel Approaches for Improving the Power Consumption Models in Correlation Analysis. IACR Cryptol. ePrint Arch. 2007: 306 (2007) - 2006
- [c2]Thanh-Ha Le, Jessy Clédière, Cécile Canovas, Bruno Robisson, Christine Servière, Jean-Louis Lacoume:
A Proposition for Correlation Power Analysis Enhancement. CHES 2006: 174-186 - 2005
- [c1]Alain Merle, Jessy Clédière:
Security Testing for Hardware Products: The Security Evaluations Practice. IOLTS 2005: 122-125 - [i1]Cécile Canovas, Jessy Clédière:
What do S-boxes Say in Differential Side Channel Attacks? IACR Cryptol. ePrint Arch. 2005: 311 (2005)
Coauthor Index
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