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ORCIDAshish Kumar 0001
Person information
- affiliation: STMicroelectronics, Greater Noida, UP, India
Other persons with the same name
- Ashish Kumar — disambiguation page
- Ashish Kumar 0002
![[0000-0002-7075-5930]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0002-7075-5930")
— Karolinska Institutet, Stockholm, Sweden (and 2 more) - Ashish Kumar 0003 — Manipal University Jaipur, Department of Computer Science and Engineering, India
- Ashish Kumar 0004 — Indian Institute of Technology Madras, Chennai, India
- Ashish Kumar 0005 — Bennett University, Department of Electronics and Communication Engineering, Greater Noida, India
- Ashish Kumar 0006 — Indian Institute of Technology Kanpur, Department of Electrical Engineering, Kanpur, India
- Ashish Kumar 0007 — University of California Berkeley, Department of Electrical Engineering and Computer Science, Berkeley, CA, USA (and 1 more)
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2010 – 2019
- 2017
[j1]Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065-mm2 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB. IEEE J. Solid State Circuits 52(7): 1927-1939 (2017)- 2016
- [c3]Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik:
A 0.065mm2 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB. ESSCIRC 2016: 165-168
2000 – 2009
- 2008
- [c2]Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. CICC 2008: 305-308 - 2007
- [c1]Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process. CICC 2007: 189-192
Coauthor Index
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