"A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed ..."

Pratap Narayan Singh et al. (2008)

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DOI: 10.1109/CICC.2008.4672082

access: closed

type: Conference or Workshop Paper

metadata version: 2018-05-30

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Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik:
A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process. CICC 2008: 305-308

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