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Journal Articles
- 1998
[j2]Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino:
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. IEEE J. Solid State Circuits 33(11): 1682-1689 (1998)- 1995
- [j1]Lavi Lev, Andy Charnas, Marc Tremblay, Alexander Dalal, Bruce A. Frederick, Chakra R. Srivatsa, David Greenhill, Dennis L. Wendell, Duy Dinh Pham, Eric Anderson, Hemraj K. Hingarh, Inayat Razzack, James M. Kaku, Ken Shin, Marc E. Levitt, Michael Allen, Philip A. Ferolito, Richard L. Bartolotti, Robert K. Yu, Ronald J. Melanson, Shailesh I. Shah, Sophie Nguyen, Sundari S. Mitra, Vinita Reddy, Vidyasagar Ganesan, Willem J. de Lange:
A 64-b microprocessor with multimedia support. IEEE J. Solid State Circuits 30(11): 1227-1238 (1995)
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