"64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency."

Raymond A. Heald et al. (1998)

> Home

Details and statistics

DOI: 10.1109/4.726558

access: closed

type: Journal Article

metadata version: 2022-07-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/HealdSRKKLLP98
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/HealdSRKKLLP98
Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino:
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. IEEE J. Solid State Circuits 33(11): 1682-1689 (1998)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.