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Journal Articles
- 2000
[j6]Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35(4): 564-571 (2000)- [j5]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma:
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. IEEE J. Solid State Circuits 35(8): 1159-1168 (2000) - 1998
- [j4]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma:
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. IEEE J. Solid State Circuits 33(11): 1650-1658 (1998) - 1996
- [j3]Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta:
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31(10): 1443-1450 (1996) - 1995
- [j2]Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma:
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. IEEE J. Solid State Circuits 30(4): 491-499 (1995) - 1994
- [j1]Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima:
A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates. IEEE J. Solid State Circuits 29(4): 419-425 (1994)
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