"A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM."

Hiroaki Nambu et al. (1998)

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DOI: 10.1109/4.726553

access: closed

type: Journal Article

metadata version: 2022-07-05

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Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma:
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. IEEE J. Solid State Circuits 33(11): 1650-1658 (1998)

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