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ORCIDYoshinori Takano
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2000 – 2009
- 2002
[j5]Toru Tanzawa
, Yoshinori Takano, Kentaro Watanabe, Shigeru Atsumi:
High-voltage transistor scaling circuit techniques for high-density negative-gate channel-erasing NOR flash memories. IEEE J. Solid State Circuits 37(10): 1318-1325 (2002)- [j4]Toru Tanzawa, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi:
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. IEEE J. Solid State Circuits 37(11): 1485-1492 (2002) - 2001
- [j3]Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi:
Wordline voltage generating system for low-power low-voltage flash memories. IEEE J. Solid State Circuits 36(1): 55-63 (2001) - 2000
- [j2]Toru Tanzawa, Yoshinori Takano, Tadayuki Taura, Shigeru Atsumi:
Design of a sense circuit for low-voltage flash memories. IEEE J. Solid State Circuits 35(10): 1415-1421 (2000) - [j1]Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe:
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE J. Solid State Circuits 35(11): 1648-1654 (2000)
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