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ORCIDTakeshi Miyaba
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2010 – 2019
- 2014
[c2]Yuji Satoh, Hiroyuki Kobayashi, Takeshi Miyaba, Shouhei Kousai:
A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration. VLSIC 2014: 1-2- 2013
- [c1]Jun Deguchi, Fumihiko Tachibana, Makoto Morimoto, Masayoshi Chiba, Takeshi Miyaba, Hideki Tanaka, Kyoichi Takenaka, Satoshi Funayama, Kunihiko Amano, Kazuhide Sugiura, Ryuta Okamoto, Shouhei Kousai:
A 187.5µVrms-read-noise 51mW 1.4Mpixel CMOS image sensor with PMOSCAP column CDS and 10b self-differential offset-cancelled pipeline SAR-ADC. ISSCC 2013: 494-495
2000 – 2009
- 2002
- [j4]Toru Tanzawa
, Akira Umezawa, Tadayuki Taura, Hitoshi Shiga, Tokumasa Hara, Yoshinori Takano, Takeshi Miyaba, Naoya Tokiwa, Kentaro Watanabe, Hiroshi Watanabe, Kazunori Masuda, Kiyomi Naruke, Hideo Kato, Shigeru Atsumi:
A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. IEEE J. Solid State Circuits 37(11): 1485-1492 (2002) - 2001
- [j3]Toru Tanzawa, Akira Umezawa, Masao Kuriyama, Tadayuki Taura, Hironori Banba, Takeshi Miyaba, Hitoshi Shiga, Yoshinori Takano, Shigeru Atsumi:
Wordline voltage generating system for low-power low-voltage flash memories. IEEE J. Solid State Circuits 36(1): 55-63 (2001) - 2000
- [j2]Shigeru Atsumi, Akira Umezawa, Tooru Tanzawa, Tadayuki Taura, Hitoshi Shiga, Yoshinori Takano, Takeshi Miyaba, Michiharu Matsui, Hiroshi Watanabe, Kazuaki Isobe, Shota Kitamura, Seiji Yamada, Masanobu Saito, Seiichi Mori, Toshiharu Watanabe:
A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE J. Solid State Circuits 35(11): 1648-1654 (2000)
1990 – 1999
- 1999
- [j1]Hironori Banba, Hitoshi Shiga, Akira Umezawa, Takeshi Miyaba, Toru Tanzawa, Shigeru Atsumi, Koji Sakui:
A CMOS bandgap reference circuit with sub-1-V operation. IEEE J. Solid State Circuits 34(5): 670-674 (1999)
Coauthor Index
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