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ORCIDRajesh Mittal
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2010 – 2019
- 2018
[c7]Mudasir S. Kawoosa, Rajesh K. Mittal, Maheedhar Jalasuthram, Rubin A. Parekhji:
Towards Single Pin Scan for Extremely Low Pin Count Test. VLSID 2018: 97-102- 2014
- [c6]Rajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji:
Systematic approach for trim test time optimization: Case study on a multi-core RF SOC. ITC 2014: 1-9 - 2013
- [c5]Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji:
Towards adaptive test of multi-core RF SoCs. DATE 2013: 743-748 - [c4]Prabhat Mishra, Masahiro Fujita, Virendra Singh, Nagesh Tamarapalli, Sharad Kumar, Rajesh Mittal:
Tutorial T10: Post - Silicon Validation, Debug and Diagnosis. VLSI Design 2013 - 2011
- [c3]Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji:
DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. ITC 2011: 1-10 - [c2]Prakash Narayanan, Rajesh Mittal, Sumanth Poddutur, Vivek Singhal, Puneet Sabbarwal:
Modified flip-flop architecture to reduce hold buffers and peak power during scan shift operation. VTS 2011: 154-159 - 2010
- [c1]Rajesh Mittal, Adesh Sontakke, Rubin A. Parekhji:
Test time reduction using parallel RF test techniques. VTS 2010: 40
Coauthor Index
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