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ORCIDV. R. Devanathan
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2010 – 2019
- 2016
[c18]V. R. Devanathan, Sumant Kale:
A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapath. ITC 2016: 1-6- 2015
- [j8]Milan Patnaik
, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti:
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12(3): 22:1-22:25 (2015) - [j7]Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti:
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11(2): 133-148 (2015) - [c17]V. R. Devanathan, Lakshmanan Balasubramanian, Rubin A. Parekhji:
New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation. VLSID 2015: 363-368 - [c16]Pavan Vithal Torvi, V. R. Devanathan, V. Kamakoti:
Framework for Selective Flip-Flop Replacement for Soft Error Mitigation. VLSID 2015: 381-386 - 2014
- [c15]Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti:
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID 2014: 342-347 - 2013
- [j6]Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti:
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9(2): 207-228 (2013) - [c14]Rajesh Mittal, Lakshmanan Balasubramanian, Y. B. Chethan Kumar, V. R. Devanathan, Mudasir Kawoosa, Rubin A. Parekhji:
Towards adaptive test of multi-core RF SoCs. DATE 2013: 743-748 - 2012
- [j5]Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti:
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8(5): 684-695 (2012) - 2011
- [c13]V. R. Devanathan, Sunil Bhavsar, Rajat Mehrotra:
Physical-Aware Memory BIST Datapath Synthesis: Architecture and Case-Studies on Complex SoCs. Asian Test Symposium 2011: 457-458 - [c12]V. R. Devanathan, Srinivas Kumar Vooka:
Techniques to improve memory interface test quality for complex SoCs. ITC 2011: 1-10 - [c11]V. R. Devanathan, Ishaan Santhosh Shah:
Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. VLSI Design 2011: 262-267 - 2010
- [j4]M. A. Maluk Mohamed, V. R. Devanathan, D. Janakiram:
EOMP: an exactly once multicast protocol for distributed mobile systems. Int. J. Parallel Emergent Distributed Syst. 25(3): 183-207 (2010) - [c10]V. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar:
Towards effective and compression-friendly test of memory interface logic. ITC 2010: 124-133
2000 – 2009
- 2008
- [j3]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4(1): 101-110 (2008) - 2007
- [j2]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24(4): 374-384 (2007) - [c9]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE 2007: 534-539 - [c8]Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji:
Methodology for low power test pattern generation using activity threshold control logic. ICCAD 2007: 526-529 - [c7]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC 2007: 1-10 - [c6]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC 2007: 1-9 - [c5]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356 - [c4]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007: 167-172 - 2006
- [j1]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2(3): 464-476 (2006) - 2005
- [c3]V. R. Devanathan:
Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage. Asian Test Symposium 2005: 300-305 - [c2]C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar:
A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design 2005: 497-503 - 2003
- [c1]D. Janaki Ram, M. A. Maluk Mohamed, V. R. Devanathan:
A Framework for Concurrency Control in Real-Time Distributed Collaboration for Mobile Systems. ICDCS Workshops 2003: 488-492
Coauthor Index
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