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ORCIDHongyu Chen 0001
Person information
- affiliation: University of California, San Diego, La Jolla, CA, USA
Other persons with the same name
- Hongyu Chen — disambiguation page
- Hongyu Chen 0002
![[0000-0003-4317-7554]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0003-4317-7554")
— Greater Bay Area Institute of Precision Medicine, Guangzhou, China - Hongyu Chen 0003 — China University of Geosciences, Wuhan, China
- Hongyu Chen 0004 — Southwest Jiaotong University, Chengdu, China
- Hongyu Chen 0005 — Alibaba Group, Beijing, China (and 1 more)
- Hongyu Chen 0006 — Shanghai Maritime University, Shanghai, China
- Hongyu Chen 0007 — Hong Kong Polytechnic University, Hong Kong, SAR, China
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2010 – 2019
- 2011
[j4]Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 520-524 (2011)
2000 – 2009
- 2007
- [j3]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 959-969 (2007) - [c18]Haikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen:
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ASP-DAC 2007: 684-689 - [c17]Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng:
Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. ISQED 2007: 251-256 - 2006
- [c16]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78 - [c15]Yuanfang Hu, Yi Zhu, Hongyu Chen, Ronald L. Graham, Chung-Kuan Cheng:
Communication latency aware low power NoC synthesis. DAC 2006: 574-579 - 2005
- [j2]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y architecture for on-chip interconnect: analysis and methodology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 588-599 (2005) - [c14]Hongyu Chen, Chung-Kuan Cheng:
A multi-level transmission line network approach for multi-giga hertz clock distribution. ASP-DAC 2005: 103-106 - [c13]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 - [c12]Yuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng:
Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style Optimizationz. ICCD 2005: 111-118 - [c11]Hongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris:
Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip Communications. ICCD 2005: 497-502 - [c10]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris:
Unified quadratic programming approach for mixed mode placement. ISPD 2005: 193-199 - 2004
- [c9]Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng:
A multiple level network approach for clock skew minimization with process variations. ASP-DAC 2004: 263-268 - [c8]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Makoto Mori, Qinke Wang:
Optimal planning for mesh-based power distribution. ASP-DAC 2004: 444-449 - 2003
- [j1]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Floorplan representations: Complexity and connections. ACM Trans. Design Autom. Electr. Syst. 8(1): 55-80 (2003) - [c7]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
The Y-architecture: yet another on-chip interconnect solution. ASP-DAC 2003: 840-847 - [c6]Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu:
An algebraic multigrid solver for analytical placement with layout based clustering. DAC 2003: 794-799 - [c5]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao:
The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. ICCAD 2003: 13-20 - [c4]Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang:
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. SLIP 2003: 71-76 - 2002
- [c3]Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng:
Physical Planning Of On-Chip Interconnect Architectures. ICCD 2002: 30-35 - [c2]Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng:
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. SLIP 2002: 85-89 - 2001
- [c1]Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham:
Revisiting floorplan representations. ISPD 2001: 138-143
Coauthor Index
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