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James Jacob
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2010 – 2019
- 2016
- [j7]Debabrata Ray, Mukunda Dev Behera, James Jacob:
Improving spatial transferability of ecological niche model of Hevea brasiliensis using pooled occurrences of introduced ranges in two biogeographic regions of India. Ecol. Informatics 34: 153-163 (2016)
2000 – 2009
- 2000
- [j6]Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik:
Line coverage of path delay faults. IEEE Trans. Very Large Scale Integr. Syst. 8(5): 610-614 (2000)
1990 – 1999
- 1998
- [c15]Pramit Chavda, James Jacob, Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221 - [c14]P. Srinivasa Rao, James Jacob:
A Fast Two-level Logic Minimizer. VLSI Design 1998: 528-533 - 1997
- [c13]James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal:
Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design 1997: 514-515 - 1996
- [j5]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(7): 831-843 (1996) - [j4]Ananta K. Majhi, James Jacob, Lalit M. Patnaik:
A Novel Path Delay Fault Simulator Using Binary Logic. VLSI Design 4(3): 167-179 (1996) - [c12]Anil K. Chaudhay, Jacob Augustine, James Jacob:
Lossless Compression Of Images Using Logic Minimization. ICIP (1) 1996: 77-80 - [c11]Nripendra N. Biswas, C. Srikanth, James Jacob:
Cubical CAMP for minimization of Boolean functions. VLSI Design 1996: 264-269 - [c10]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
On test coverage of path delay faults. VLSI Design 1996: 418-421 - 1995
- [j3]Jacob Augustine, Wen Feng, Anamitra Makur, James Jacob:
Switching theoretic approach to image compression. Signal Process. 44(2): 243-246 (1995) - [c9]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Functional test generation for non-scan sequential circuits. VLSI Design 1995: 47-52 - [c8]Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal:
An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165 - [c7]Jacob Augustine, Wen Feng, James Jacob:
Logic minimization based approach for compressing image data. VLSI Design 1995: 225-228 - 1994
- [c6]P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal:
An Improved Deductive Fault Simulator. VLSI Design 1994: 307-310 - 1993
- [c5]P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob:
Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. VLSI Design 1993: 104 - 1992
- [j2]James Jacob, Vishwani D. Agrawal:
Multiple fault detection in two-level multi-output circuits. J. Electron. Test. 3(2): 171-173 (1992) - [c4]Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal:
Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS 1992: 238-245 - [c3]James Jacob, Vishwani D. Agrawal:
Functional Test Generation for Sequential Circuits. VLSI Design 1992: 17-24 - [c2]Oommen Tharakan, James Jacob, Mandyam-Komar Srinivas:
An Efficient Rule Based Fault Simulator. VLSI Design 1992: 154-156 - 1990
- [j1]James Jacob, Nripendra N. Biswas:
Further Comments on "Detection of Faults in Programmable Logic Arrays". IEEE Trans. Computers 39(1): 155-157 (1990)
1980 – 1989
- 1985
- [c1]James Jacob, Nripendra N. Biswas:
: A Testable PLA Design with Minimal Hardware and Test Set. ITC 1985: 583-588
Coauthor Index
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