"Optimizing Logic Design Using Boolean Transforms."

Pramit Chavda, James Jacob, Vishwani D. Agrawal (1998)

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DOI: 10.1109/ICVD.1998.646605

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Pramit Chavda, James Jacob, Vishwani D. Agrawal:
Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221

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