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Michal Kekely
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Books and Theses
- 2024
- [b1]Michal Kekely:
Mapování zpracování paketů popsaného v jazyce P4 do technologie FPGA ; Mapping of packet processing from P4 Language to FPGA Technology. Brno University of Technology, Czech Republic, 2024
Journal Articles
- 2020
- [j1]Michal Kekely, Lukás Kekely, Jan Korenek:
General memory efficient packet matching FPGA architecture for future high-speed networks. Microprocess. Microsystems 73: 102950 (2020)
Conference and Workshop Papers
- 2023
- [c8]Michal Kekely, Jan Korenek:
Optimizing Packet Classification on FPGA. DDECS 2023: 7-12 - 2020
- [c7]Tomás Benes, Michal Kekely, Karel Hynek, Tomás Cejka:
Pipelined ALU for effective external memory access in FPGA. DSD 2020: 97-100 - 2018
- [c6]Zdenek Martinasek, Jan Hajny, David Smekal, Lukas Malina, Denis Matousek, Michal Kekely, Nele Mentens:
200 Gbps Hardware Accelerated Encryption System for FPGA Network Cards. ASHES@CCS 2018: 11-17 - [c5]Michal Kekely, Lukas Kekely, Jan Korenek:
Memory Aware Packet Matching Architecture for High-Speed Networks. DSD 2018: 1-8 - [c4]Jakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek:
Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. FPGA 2018: 249-258 - 2017
- [c3]Michal Kekely, Jan Korenek:
Packet Classification with Limited Memory Resources. DSD 2017: 179-183 - [c2]Pavel Benácek, Viktor Pus, Jan Korenek, Michal Kekely:
Line rate programmable packet processing in 100Gb networks. FPL 2017: 1 - [c1]Michal Kekely, Jan Korenek:
Mapping of P4 match action tables to FPGA. FPL 2017: 1-2
Coauthor Index
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