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2020 – today
- 2024
[c13]Swaminathan Sankaran, Gerd Schuppener, Juan Herbsommer, Bradley Kramer, Hassan Ali, Robert Payne, Carole Rush, Baher Haroun, Nirmal Warke:
A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links. MWSCAS 2024: 1026-1032
2010 – 2019
- 2015
- [c12]Swaminathan Sankaran, Bradley Kramer, Gregory Howard, Benjamin Sutton, Randall Walberg, Vijaylaxmi Khanolkar, Robert Payne, Mark Morgan:
An efficient and resilient ultra-high speed galvanic data isolator leveraging broad-band multi resonant tank electro-magnetic coupling. VLSIC 2015: 210- - 2014
- [j5]Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright:
A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. IEEE J. Solid State Circuits 49(9): 1876-1885 (2014) - 2013
- [j4]Yuxiang Zheng, Jin Liu, Robert Payne, Mark Morgan, Hoi Lee:
A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2274-2285 (2013) - [c11]Xiaochen Yang, Robert Payne, Jin Liu:
A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. CICC 2013: 1-4 - 2012
- [c10]Robert Payne, Tatsuya Saito:
Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee. ISSCC 2012: 128-129 - 2011
- [c9]Robert Payne, Charles K. Sestok, William Bright, Manar El-Chammas, Marco Corsi, David Smith, Noam Tal:
A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. ISSCC 2011: 182-184 - [c8]Jerry Lin, Franz Dielacher
, Jing-Hong Conan Zhan, Robert Payne:
Good, bad, ugly - 20 years of broadband evolution: What's next? ISSCC 2011: 525 - 2010
- [j3]Robert Payne, Marco Corsi, David Smith, Tien-Ling Hsieh, Scott Kaylor:
A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. IEEE J. Solid State Circuits 45(12): 2613-2622 (2010) - [c7]Robert Payne, Marco Corsi, David Smith, Scott Kaylor, Daniel Hsieh:
A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. ISSCC 2010: 294-295 - [c6]Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne:
Energy-efficient high-speed interfaces. ISSCC 2010: 524-525
2000 – 2009
- 2009
- [c5]Hao Liu, Jin Liu, Robert Payne, Cy Cantrell, Mark Morgan:
A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. CICC 2009: 113-116 - [c4]Ali Sheikholeslami, Robert Payne:
Will ADCs overtake binary frontends in backplane signaling? ISSCC 2009: 514 - 2008
- [c3]Robert Payne:
Future of High-Speed Transceivers (Forum). ISSCC 2008: 658-659 - 2007
- [c2]Robert Payne, Muneo Fukaishi:
Multi-GB/s Transceivers. ISSCC 2007: 434-435 - 2005
- [j2]Robert Payne, Paul E. Landman, Bhavesh Bhakta, Sridhar Ramaswamy, Song Wu, John D. Powers, M. Ulvi Erdogan, Ah-Lyan Yee, Richard Gu, Lin Wu, Yiqun Xie, Bharadwaj Parthasarathy, Keith C. Brouse, Wahed Mohammed, Keerthi Heragu, Vikas Gupta, Lisa Dyson, Wai Lee:
A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels. IEEE J. Solid State Circuits 40(12): 2646-2657 (2005)
1990 – 1999
- 1999
- [c1]Richard Goering, Pierre Bricaud, James G. Dougherty, Steve Glaser, Michael Keating, Robert Payne, Davoud Samani:
Panel: What is the Proper System on Chip Design Methodology. DAC 1999: 999 - 1997
- [b1]Robert Payne:
Self-timed field programmmable gate array architectures. University of Edinburgh, UK, 1997
1960 – 1969
- 1962
- [j1]Lawrence Stark, Robert Payne, Yutaka Okabe:
Online digital computer measurement of a neurological control system. Commun. ACM 5(11): 567-568 (1962)
Coauthor Index
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