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ORCIDJulen Gomez-Cornejo
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2020 – today
- 2022
[c2]Julen Gomez-Cornejo, Igor Villalta, Itxaso Aranzabal, Iraide Lopez, Aitzol Zuloaga:
Data content scrubbing approach for SRAM based FPGA designs. ISIE 2022: 649-654
2010 – 2019
- 2018
- [j4]Igor Villalta, Unai Bidarte
, Julen Gomez-Cornejo, Jaime Jimenez, Jesús Lázaro:
SEU emulation in industrial SoCs combining microprocessor and FPGA. Reliab. Eng. Syst. Saf. 170: 53-63 (2018) - 2017
- [j3]Julen Gomez-Cornejo, Aitzol Zuloaga, Igor Villalta, Javier Del Ser, Uli Kretzschmar, Jesús Lázaro:
A novel BRAM content accessing and processing method based on FPGA configuration bitstream. Microprocess. Microsystems 49: 64-76 (2017) - [j2]Igor Villalta, Unai Bidarte, Julen Gomez-Cornejo, Jesús Lázaro, Armando Astarloa:
Estimating the SEU failure rate of designs implemented in FPGAs in presence of MCUs. Microelectron. Reliab. 78: 85-92 (2017) - 2016
- [j1]Uli Kretzschmar, Julen Gomez-Cornejo, Armando Astarloa, Unai Bidarte, Javier Del Ser:
Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs. Reliab. Eng. Syst. Saf. 151: 1-9 (2016) - 2013
- [c1]Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzschmar, Unai Bidarte, Jaime Jimenez:
Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON 2013: 2261-2266
Coauthor Index
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