default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDMicroprocessors and Microsystems, Volume 49
Volume 49, March 2017
- Renan Augusto Starke
, Andreu Carminati, Rômulo Silva de Oliveira:
Evaluation of a low overhead predication system for a deterministic VLIW architecture targeting real-time applications. 1-8 - Seyed Mohammad M. Tabei, Hooman Nikmehr:
An unsigned truncated sequential multiplier with variable error compensation. 9-17 - Jubal Saji, Shoaib Kamal:
GDI logic implementation of uniform sized CSLA architectures in 45 nm SOI technology. 18-27 - Atef Dorai, Virginie Fresse, Catherine Combes, El-Bay Bourennane, Abdellatif Mtibaa:
A collision management structure for NoC deployment on multi-FPGA. 28-43 - Wen Wen, Jun Yang, Youtao Zhang:
Optimizing power efficiency for 3D stacked GPU-in-memory architecture. 44-53 - Antonio Lopes Filho, Roberto d'Amore:
A tolerant JPEG-LS image compressor foreseeing COTS FPGA implementation. 54-63 - Julen Gomez-Cornejo, Aitzol Zuloaga, Igor Villalta, Javier Del Ser, Uli Kretzschmar, Jesús Lázaro:
A novel BRAM content accessing and processing method based on FPGA configuration bitstream. 64-76 - Darío Baptista, Sandy Abreu, Carlos M. Travieso-González, Fernando Morgado Dias:
Hardware implementation of an artificial neural network model to predict the energy production of a photovoltaic system. 77-86 - Aboli Audumbar Khedkar, R. H. Khade:
High speed FPGA-based data acquisition system. 87-94 - Joonho Kong, Young-Ho Gong, Sung Woo Chung:
Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme. 95-104 - John V. Vourvoulakis, John A. Kalomiros, John N. Lygouras:
FPGA accelerator for real-time SIFT matching with RANSAC support. 105-116 - Ruilian Xie, Jueping Cai, Xin Xin, Bo Yang:
MCAR: Non-local adaptive Network-on-Chip routing with message propagation of congestion information. 117-126 - Amir Mokhtar Chabi, Arman Roohi, Hossein Khademolhosseini, Shadi Sheikhfaal, Shaahin Angizi, Keivan Navi, Ronald F. DeMara:
Towards ultra-efficient QCA reversible circuits. 127-138 - Fahimeh Yazdanpanah:
An approach for analyzing auto-vectorization potential of emerging workloads. 139-149 - Imtiaz Ahmad, Areej Hamouda, Mohammad AlFailakawi:
Odd/Even Invert coding for phase change memory with thermal crosstalk. 150-163 - Hisham Ahmed, Othman Sidek:
An energy-aware self-adaptive System-on-Chip architecture for real-time Harris corner detection with multi-resolution support. 164-178 - Farid Shamani, Vida Fakour Sevom, Tapani Ahonen, Jari Nurmi:
Integration issues of a run-time configurable memory management unit to a RISC processor on FPGA. 179-191
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-15 00:19 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
