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Pietro Buccella

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affiliation: École Polytechnique Fédérale de Lausanne, Switzerland

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Journal Articles

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2016
[j1]
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  - journals/tcad/BuccellaSZMISK16
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  - https://dblp.org/rec/journals/tcad/BuccellaSZMISK16
Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal:
Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(9): 1489-1502 (2016)

Conference and Workshop Papers

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2018
[c12]
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  - conf/newcas/RossiBSS18
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Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese:
Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics. NEWCAS 2018: 35-39
2017
[c11]
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Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese:
SPICE modeling of light induced current in silicon with 'Generalized' lumped devices. ESSDERC 2017: 26-29
[c10]
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  - conf/newcas/GosselinBKK17
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Paul Gosselin, Pietro Buccella, Adil Koukab, Maher Kayal:
Toward low-power PPG-based heart rate monitoring using a MOS-PN hybrid photosensor. NEWCAS 2017: 141-144
[c9]
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  - conf/newcas/RipamontiMBKK17
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Giacomo Ripamonti, Stefano Michelis, Pietro Buccella, Adil Koukab, Maher Kayal:
Substrate-currents-aware characterization of an integrated buck DC/DC converter for floor-plan optimization. NEWCAS 2017: 169-172
2016
[c8]
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  - conf/essderc/StefanucciBSSKS16
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Camillo Stefanucci, Pietro Buccella, Ehrenfried Seebacher, Alexander Steinmair, Maher Kayal, Jean-Michel Sallese:
Analysis of substrate currents propagation in HVCMOS technology. ESSDERC 2016: 319-322
[c7]
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  - conf/mixdes/BuccellaSSK16
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Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal:
Active guard ring characterization for Smart Power ICs. MIXDES 2016: 305-309
2015
[c6]
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  - conf/dtis/StefanucciBKS15
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Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Modeling avalanche breakdown for ESD diodes in integrated circuits. DTIS 2015: 1-3
[c5]
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  - conf/iscas/ZouMISBKS15
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Hao Zou, Yasser Moursy, Ramy Iskander, Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Substrate noise modeling with dedicated CAD framework for smart power ICs. ISCAS 2015: 1554-1557
[c4]
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Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Modeling parasitic vertical PNP in HVCMOS. MIXDES 2015: 486-489
[c3]
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Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal:
Spice simulation of passive protection in smart power ICs. MIXDES 2015: 500-503
2014
[c2]
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Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese:
Optimization strategy of numerical simulations applied to EPFL substrate model. MIXDES 2014: 334-337
[c1]
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Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal:
Spice simulation of substrate minority carriers propagation with equivalent electrical circuit. MIXDES 2014: 347-350

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