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2020 – today
- 2023
[c8]Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Manui Avodhyawasi, Harsh Rawat, Hitesh Chawla, VS Abhijith, Paolo Zambotti, Akhilesh Sharma, Carmine Cappetta, Michele Rossi, Antonio De Vita, Francesca Girardi:
A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications. ISSCC 2023: 260-261- [c7]Belal Iqbal, Anuj Grover, Harsh Rawat:
A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute Applications in 65nm LSTP Technology. VLSID 2023: 121-126 - 2022
- [c6]Belal Iqbal, Anuj Grover, Harsh Rawat:
A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators. AICAS 2022: 459-462 - [c5]Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. ISCAS 2022: 1546-1550 - [c4]Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat:
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. VLSID 2022: 228-233 - 2021
- [c3]Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. ICECS 2021: 1-6
2010 – 2019
- 2017
- [c2]Harsh Rawat, K. Bharath, Alexander Fell
:
Asynchronous 1R-1W dual-port SRAM by using single-port SRAM in 28nm UTBB-FDSOI technology. SoCC 2017: 1-6 - 2015
- [j2]Amit Chhabra, Harsh Rawat, Mohit Jain, Pascal Tessier, Daniel Pierredon, Laurent Bergher, Promod Kumar:
FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(7): 1138-1142 (2015) - [c1]Ramandeep Kaur, Alexander Fell, Harsh Rawat:
A 6T SRAM cell based pipelined 2R/1W memory design using 28nm UTBB-FDSOI. SoCC 2015: 310-315 - 2014
- [j1]Kedar Janardan Dhori, Vinay Kumar, Harsh Rawat:
Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2350-2356 (2014)
Coauthor Index
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