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ORCIDKedar Janardan Dhori
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2020 – today
- 2022
[c10]Mukesh Kumar Srivastav, Rimjhim, Roshan Mishra, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
3-Stage Pipelined Hierarchical SRAMs with Burst Mode Read in 65nm LSTP CMOS. ISCAS 2022: 1546-1550- [c9]Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet:
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. VLSID 2022: 216-221 - [c8]Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat:
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. VLSID 2022: 228-233 - 2021
- [c7]Sylvain Clerc, Kedar Janardan Dhori, Robin M. Wilson, Rohit Goel, Sébastien Marchal, Franck Pourchon, Christian Dutto, Ricardo Gomez Gomez:
Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS technologies. ESSCIRC 2021: 271-274 - [c6]Mukesh Kumar Srivastav, Rimjhim, Govind Soni, Umang Mittal, Rupali Tewari, Riya Yadav, Anuj Grover, Kedar Janardan Dhori, Harsh Rawat:
Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. ICECS 2021: 1-6 - 2020
- [c5]Shivendra Singh, Varshita Gupta, Anuj Grover
, Kedar Janardan Dhori:
Diagnostic Circuit for Latent Fault Detection in SRAM Row Decoder. ISQED 2020: 395-400
2010 – 2019
- 2017
- [c4]Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain:
High-yield design of high-density SRAM for low-voltage and low-leakage operations. DFT 2017: 1-6 - 2016
- [c3]Amit Chhabra, Mudit Srivastava, Prakhar Raj Gupta, Kedar Janardan Dhori, Philippe Triolet, Thierry Di Gilio, Nitin Bansal, B. Sujatha:
Temperature-based adaptive memory sub-system in 28nm UTBB FDSOI. ISCAS 2016: 1018-1021 - 2015
- [c2]Ashish Kumar, Vinay Kumar, Dhori Kedar Janardan, G. S. Visweswaran, Kaushik Saha:
A 6T-SRAM in 28nm FDSOI technology with Vmin of 0.52V using assisted read and write operation. ICICDT 2015: 1-4 - [c1]Kedar Janardan Dhori, Vinay Kumar, Ashish Kumar:
A CMOS 90nm 50Mhz Supply Noise Tolerant High Density 8T-NAND ROM. VLSID 2015: 181-185 - 2014
- [j1]Kedar Janardan Dhori, Vinay Kumar, Harsh Rawat:
Write Assist Circuit to Cater Reliability and Floating Bit Line Problem of Negative Bit Line Assist Technique for Single or Multiport Static Random Access Memory. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2350-2356 (2014)
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