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ORCIDMaciej Kopczynski
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2020 – today
- 2024
[c14]Maciej Kopczynski
:
Usage of Real-World Maps for 3D Mobile Games - Transformations and Optimizations. CISIM 2024: 387-400- [c13]Maciej Kopczynski:
World Maps Conversions for 3D Mobile Games Working in Real-Time Environment. ISD 2024 - 2022
- [j5]Maciej Kopczynski, Tomasz Grzes:
FPGA supported rough set reduct calculation for big datasets. J. Intell. Inf. Syst. 59(3): 779-799 (2022) - [c12]Maciej Kopczynski:
Mobile Phone as a 6DoF Motion Controller. CISIM 2022: 345-359 - 2021
- [j4]Maciej Kopczynski, Tomasz Grzes:
Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets. J. Artif. Intell. Soft Comput. Res. 11(2): 99-110 (2021) - [c11]Michal Czolombitko, Tomasz Grzes, Maciej Kopczynski, Urszula Kuzelewska, Anna Lupinska-Dubicka, Dorota Mozyrska, Joanna Panasiuk:
Development of Digital Competences of Elementary School Teachers with a Life-Long Learning Approach. CISIM 2021: 100-111 - [c10]Maciej Kopczynski:
FPGA in Core Calculation for Big Datasets. CISIM 2021: 406-417 - 2020
- [c9]Maciej Kopczynski, Tomasz Grzes:
Parallelized Hardware Rough Set Processor Architecture in FPGA for Core Calculation in Big Datasets. ICARCV 2020: 1098-1103
2010 – 2019
- 2019
- [c8]Tomasz Grzes, Maciej Kopczynski:
Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. IJCRS 2019: 495-506 - 2017
- [c7]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Hardware Supported Rule-Based Classification on Big Datasets. IJCRS (1) 2017: 655-668 - 2016
- [j3]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Core for Large Datasets: Rough Sets on FPGA. Fundam. Informaticae 147(2-3): 241-259 (2016) - [j2]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Rough Sets Based LEM2 Rules Generation Supported by FPGA. Fundam. Informaticae 148(1-2): 107-122 (2016) - [c6]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Hardware Supported Rough Sets Based Rules Generation for Big Datasets. CISIM 2016: 91-102 - 2015
- [c5]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Core for Large Datasets: Rough Sets on FPGA. CS&P 2015: 235-246 - [c4]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Computation of Cores in Big Datasets: An FPGA Approach. RSKT 2015: 153-163 - 2014
- [c3]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
Generating Core in Rough Set Theory: Design and Implementation on FPGA. RSEISP 2014: 209-216 - [c2]Maciej Kopczynski, Tomasz Grzes, Jaroslaw Stepaniuk:
FPGA in Rough-Granular Computing: Reduct Generation. WI-IAT (1) 2014: 364-370 - 2013
- [j1]Jaroslaw Stepaniuk, Maciej Kopczynski, Tomasz Grzes:
The First Step Toward Processor for Rough Set Methods. Fundam. Informaticae 127(1-4): 429-443 (2013) - [c1]Tomasz Grzes, Maciej Kopczynski, Jaroslaw Stepaniuk:
FPGA in Rough Set Based Core and Reduct Computation. RSKT 2013: 263-270 - [p1]Maciej Kopczynski, Jaroslaw Stepaniuk:
Hardware Implementations of Rough Set Methods in Programmable Logic Devices. Rough Sets and Intelligent Systems (2) 2013: 309-321
Coauthor Index
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last updated on 2024-11-20 21:58 CET by the dblp team
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