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ORCIDKazutaka Ikegami
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Conference and Workshop Papers
- 2019
[c9]Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami:
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. VLSI Circuits 2019: 278-- 2017
- [c8]Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT 2017: 1-2 - 2016
- [c7]Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
:
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC 2016: 132-133 - 2015
- [c6]Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita:
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC 2015: 1-3 - 2014
- [c5]Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC 2014: 316-319 - [c4]Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita:
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC 2014: 1-2 - 2012
- [c3]Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita:
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops 2012: 213-220 - 2010
- [c2]Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita:
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA 2010: 291 - 2008
- [c1]Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita:
1200μm2 Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC 2008: 414-415
Informal and Other Publications
- 2011
- [i1]Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito:
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET. CoRR abs/1104.1493 (2011)
Coauthor Index
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