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ORCIDJosé O. Cadenas
Person information
- affiliation: London South Bank University, UK
- affiliation (former): University of Reading, School of Systems Engineering, UK
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2020 – today
- 2021
[i3]Oswaldo Cadenas, Graham M. Megson:
Non-uniform quantization with linear average-case computation time. CoRR abs/2108.08228 (2021)
2010 – 2019
- 2019
- [j11]Oswaldo Cadenas
, Graham M. Megson:
Running Median Algorithm and Implementation for Integer Streaming Applications. IEEE Embed. Syst. Lett. 11(2): 58-61 (2019) - 2018
- [j10]Dawid Laszuk, José O. Cadenas, Slawomir J. Nasuto:
KurSL: Model of Anharmonic Coupled Oscillations Based on Kuramoto Coupling and Sturm-Liouville Problem. Adv. Data Sci. Adapt. Anal. 10(2): 1840002:1-1840002:23 (2018) - 2016
- [j9]Dawid Laszuk, José O. Cadenas, Slawomir J. Nasuto:
On the Phase Coupling of Two Components Mixing in Empirical Mode Decomposition. Adv. Data Sci. Adapt. Anal. 8(1): 1650004:1-1650004:11 (2016) - 2015
- [j8]José O. Cadenas, Graham M. Megson, Robert Simon Sherratt:
Median Filter Architecture by Accumulative Parallel Counters. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 661-665 (2015) - [j7]José O. Cadenas, Robert Simon Sherratt, Des Howlett, Chris G. Guy, Karsten Øster Lundqvist:
Virtualization for Cost-Effective Teaching of Assembly Language Programming. IEEE Trans. Educ. 58(4): 282-288 (2015) - [c17]Dawid Laszuk, Oswaldo Cadenas, Slawomir J. Nasuto:
Objective Empirical Mode Decomposition metric. TSP 2015: 504-507 - [i2]José O. Cadenas, Graham M. Megson:
An Empirical Evaluation of Preconditioning Data for Accelerating Convex Hull Computations. CoRR abs/1505.00914 (2015) - 2014
- [c16]Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson:
Acceleration and visualization of Dynamic Network Optimization. ICNC 2014: 726-730 - 2013
- [j6]Graham M. Megson, José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao:
A Parallel Quantum Histogram Architecture. IEEE Trans. Circuits Syst. II Express Briefs 60-II(7): 437-441 (2013) - [j5]José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson:
C-slow retimed parallel histogram architectures for consumer imaging devices. IEEE Trans. Consumer Electron. 59(2) (2013) - [c15]José O. Cadenas, R. Simon Sherratt, Pablo Huerta, Wen-Chung Kao, Graham M. Megson:
Parallel pipelined histogram architecture via C-slow retiming. ICCE 2013: 230-231 - [c14]Yuanzhou Ye, Oswaldo Cadenas, Graham M. Megson:
Distributed parallelization of greedy Mobile Network Optimization algorithms. SoftCOM 2013: 1-5 - [c13]Yuanzhou Ye, Graham M. Megson, Oswaldo Cadenas:
Asynchronous distributed parallelization of mobile network optimization algorithms. VITAE 2013: 1-6 - [i1]Graham M. Megson, José O. Cadenas:
A Rank-based Convex Hull method for Dense Data Sets. CoRR abs/1301.4809 (2013) - 2011
- [j4]José O. Cadenas, Robert Simon Sherratt, Pablo Huerta, Wen-Chung Kao:
Parallel pipelined array architectures for real-time histogram computation in consumer devices. IEEE Trans. Consumer Electron. 57(4): 1460-1464 (2011) - 2010
- [j3]Robert Simon Sherratt, José O. Cadenas:
A double data rate architecture for OFDM based wireless consumer devices. IEEE Trans. Consumer Electron. 56(1): 23-26 (2010)
2000 – 2009
- 2006
- [c12]Oswaldo Cadenas, Graham M. Megson:
Verification and FPGA Circuits of a Block-2 Fast Path-Based Predictor. FPL 2006: 1-6 - 2005
- [j2]Robert Simon Sherratt, Oswaldo Cadenas, Nomita Goswami:
A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers. IEEE Trans. Consumer Electron. 51(3): 798-802 (2005) - [c11]Oswaldo Cadenas, Graham M. Megson, Daniel Jones:
Implementation of a block based neural branch predictor. DSD 2005: 235-238 - [c10]Oswaldo Cadenas, Graham M. Megson, Daniel Jones:
FPGA Organization for the Fast Path-Based Neural Branch Predictor. FPT 2005: 251-258 - [c9]Oswaldo Cadenas, Graham M. Megson, Daniel Jones:
A New Organization for a Perceptron-Based Branch Predictor and Its FPGA Implementation. ISVLSI 2005: 305-306 - 2004
- [j1]Oswaldo Cadenas, Graham M. Megson:
A clocking technique for FPGA pipelined designs. J. Syst. Archit. 50(11): 687-696 (2004) - [c8]Oswaldo Cadenas, Graham M. Megson:
A FPGA pipelined backward adaptive scalar quantizer. Circuits, Signals, and Systems 2004: 410-415 - 2003
- [c7]Oswaldo Cadenas, Graham M. Megson, Toomas P. Plaks:
FPGA Circuits for a Monte-Carlo Based Matrix Inversion Architecture. Engineering of Reconfigurable Systems and Algorithms 2003: 201-207 - [c6]Oswaldo Cadenas, Graham M. Megson:
Pullpipelining: A technique for systolic pipelined circuits. IWSOC 2003: 205-210 - 2002
- [c5]Oswaldo Cadenas, Graham M. Megson:
Improving mW/MHz Ratio in FPGAs Pipelined Designs. DSD 2002: 276-282 - [c4]Oswaldo Cadenas, Graham M. Megson:
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. FPL 2002: 322-331 - 2001
- [c3]Oswaldo Cadenas, Graham M. Megson:
Pipelining Considerations for an FPGA Case. DSD 2001: 276-285 - [c2]Oswaldo Cadenas, Graham M. Megson:
A n-Bit Reconfigurable Scalar Quantiser. FPL 2001: 420-429
1990 – 1999
- 1999
- [c1]Toomas P. Plaks, Oswaldo Cadenas, Graham M. Megson:
Experiences Using Reconfigurable FPGAs in Implementing Monte-Carlo Methods. PDPTA 1999: 1131-1137
Coauthor Index
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