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ORCIDSheng Liu 0001
Person information
- affiliation: National University of Defense Technology, School of Computer, Changsha, China
Other persons with the same name
- Sheng Liu — disambiguation page
- Sheng Liu 0002
![[0000-0001-8082-0903]](https://dblp.uni-trier.de./img/orcid-mark.12x12.png "0000-0001-8082-0903")
— Zhejiang University of Technology, College of Computer Science and Technology, Hangzhou, China - Sheng Liu 0003 — Chinese Academy of Sciences, Institute of Automation, State Key Laboratory of Management and Control for Complex Systems, Beijing, China (and 2 more)
- Sheng Liu 0004 — South China Normal University, Laboratory of Quantum Engineering and Quantum Materials, Guangzhou, China
- Sheng Liu 0005 — Huaibei Normal University, College of Computer Science and Technology, China (and 1 more)
- Sheng Liu 0006 — University of California Berkeley, Department of Industrial Engineering and Operations Research, CA, USA
- Sheng Liu 0007 — Shanghai University of Engineering Science, School of Management, Shanghai, China (and 1 more)
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2020 – today
- 2024
[c18]Lanting Guo, Haiyan Chen, Chen Li, Sheng Liu:
LWECC: A Lightweight ECC Technology for HPC Accelerators Supporting Multi-granularity Memory Access. ISCAS 2024: 1-5- 2023
- [j14]Tiehang Duan, Zhenyi Wang, Sheng Liu, Yiyi Yin, Sargur N. Srihari:
UNCER: A framework for uncertainty estimation and reduction in neural decoding of EEG signals. Neurocomputing 538: 126210 (2023) - 2022
- [j13]Kai Lu, Yaohua Wang, Yang Guo, Chun Huang, Sheng Liu, Ruibo Wang, Jianbin Fang, Tao Tang, Zhaoyun Chen, Biwei Liu, Zhong Liu, Yuanwu Lei, Haiyan Sun:
MT-3000: a heterogeneous multi-zone processor for HPC. CCF Trans. High Perform. Comput. 4(2): 150-164 (2022) - [c17]Yasong Cao, Mei Wen, Junzhong Shen, Sheng Liu, Zhi Wang, Minjin Tang, Yahao Fang, Jianchao Yang, Renyu Yang, Yuhan Kang, Jiawei Fei:
MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. HPCC/DSS/SmartCity/DependSys 2022: 126-134 - [c16]Min Tang, Sheng Liu:
A dynamic computational memory address architecture for systolic array CNN accelerators. HPCC/DSS/SmartCity/DependSys 2022: 1314-1319 - [c15]Minjin Tang, Mei Wen, Yasong Cao, Junzhong Shen, Jianchao Yang, Jiawei Fei, Yang Guo, Sheng Liu:
Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. ICPP 2022: 18:1-18:11 - [c14]Hongli Zhong, Zhong Liu, Sheng Liu, Sheng Ma, Chen Li:
Adaptive Low-Cost Loop Expansion for Modulo Scheduling. NPC 2022: 30-41 - [i1]Tiehang Duan, Zhenyi Wang, Sheng Liu, Sargur N. Srihari, Hui Yang:
Uncertainty Detection in EEG Neural Decoding Models. CoRR abs/2201.00627 (2022) - 2021
- [j12]Yaohua Wang, Chen Li, Chang Liu, Sheng Liu, Yuanwu Lei, Jian Zhang, Yang Zhang, Yang Guo:
Advancing DSP into HPC, AI, and beyond: challenges, mechanisms, and future directions. CCF Trans. High Perform. Comput. 3(1): 114-125 (2021) - [c13]Jianfeng Cui, Kai Lu, Sheng Liu:
Sparse Matrix-Vector Multiplication Cache Performance Evaluation and Design Exploration. MASCOTS 2021: 1-7
2010 – 2019
- 2018
- [j11]Zerun Li, Yang Guo, Sheng Liu, Junyang Zhang:
A task-based multi-core allocation mechanism for packet acceleration. IEICE Electron. Express 15(12): 20180414 (2018) - [c12]Rui Song, Guozhao Zeng, Sheng Liu, Haiyan Chen:
Conflict-Free Block-with-Stride Access of 2D Storage Structure. ICA3PP (3) 2018: 618-629 - 2017
- [j10]Xiaowen Chen, Zhonghai Lu, Sheng Liu, Shuming Chen:
Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems. ACM Trans. Embed. Comput. Syst. 16(5s): 162:1-162:21 (2017) - [c11]Hongbing Tan, Haiyan Chen, Sheng Liu, Jianguo Wu:
Modeling and evaluation for gather/scatter operations in Vector-SIMD architectures. ASAP 2017: 143-148 - [c10]Hongbing Tan, Haiyan Chen, Sheng Liu, Xikun Ma, Yaqing Chi:
A Programmable Pre-emphasis Transmitter for SerDes in 40 nm CMOS. NCCET 2017: 35-44 - 2016
- [c9]Yaohua Wang, Xiaowen Chen, Dong Wang, Sheng Liu:
Dynamic Per-Warp Reconvergence Stack for Efficient Control Flow Handling in GPUs. ISVLSI 2016: 176-181 - [c8]Sheng Liu, Haiyan Chen, Jianghua Wan, Yaohua Wang:
Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs. ISVLSI 2016: 426-430 - 2015
- [c7]Chao Yang, Haiyan Chen, Sheng Liu, Sheng Ma:
A New Memory Address Transformation for Continuous-Flow FFT Processors with SIMD Extension. NCCET 2015: 51-60 - 2014
- [j9]Shuming Chen, Yaohua Wang, Sheng Liu, Jianghua Wan, Haiyan Chen, Hengzhu Liu, Kai Zhang, Xiangyuan Liu, Xi Ning:
FT-Matrix: A Coordination-Aware Architecture for Signal Processing. IEEE Micro 34(6): 64-73 (2014) - 2013
- [j8]Wei Liu, Shuming Chen, Hu Chen, Yaohua Wang, Sheng Liu, Kai Zhang, Xi Ning:
A novel QPP interleaver for parallel turbo decoder. IEICE Electron. Express 10(8): 20120795 (2013) - [j7]Yaohua Wang, Shuming Chen, Hu Chen, Jianghua Wan, Kai Zhang, Sheng Liu:
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures. IEICE Trans. Inf. Syst. 96-D(2): 365-369 (2013) - 2012
- [j6]Kai Zhang, Shuming Chen, Hu Chen, Yaohua Wang, Xiaowen Chen, Sheng Liu, Wei Liu:
CMRF: a Configurable Matrix Register File for accelerating matrix operations on SIMD processors. IEICE Electron. Express 9(4): 283-289 (2012) - [j5]Sheng Liu, Shuming Chen, Hu Chen, Yang Guo:
A novel parallel memory organization supporting multiple access types with matched memory modules. IEICE Electron. Express 9(6): 602-608 (2012) - [j4]Yaohua Wang, Shuming Chen, Kai Zhang, Jianghua Wan, Hu Chen, Sheng Liu, Xi Ning:
A cost conscious performance model for media processors. IEICE Electron. Express 9(11): 978-984 (2012) - [j3]Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu:
Control-enhanced power-SIMD. IEICE Electron. Express 9(14): 1147-1152 (2012) - [j2]Hui Yang, Shuming Chen, Tiebin Wu, Sheng Liu:
Erratum: Control-enhanced power-SIMD [IEICE Electronics Express Vol.9 (2012), No 14 pp 1147-1152]. IEICE Electron. Express 9(16): 1369 (2012) - [c6]Yaohua Wang, Kai Zhang, Jianghua Wan, Sheng Liu, Xi Ning, Shuming Chen:
Architectural Implications for SIMD Processors in the Wireless Communication Domain. HPCC-ICESS 2012: 1199-1204 - 2011
- [j1]Sheng Liu, Shuming Chen, Xi Ning, Jianghua Wan, Hu Chen, Kai Zhang, Yaohua Wang:
LP2D: a novel low-power 2D memory for sliding-window applications in vector DSPs. IEICE Electron. Express 8(24): 2106-2111 (2011) - [c5]Kai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang:
Accelerating the data shuffle operations for FFT algorithms on SIMD DSPs. ASICON 2011: 683-686 - [c4]Hu Chen, Sheng Liu, Shuming Chen:
A Novel Highly Scalable Architecture with Partially Distributed Pipeline and Hardware/Software Instruction Encoding. NAS 2011: 242-247 - [c3]Sheng Liu, Shuming Chen, Haiyan Chen, Shenggang Chen, Hu Chen:
Supporting Efficient Memory Conflicts Reduction Using the DMA Cache Technique in Vector DSPs. NAS 2011: 302-308 - [c2]Sheng Liu, Shuming Chen, Jianghua Wan, Haiyan Chen, Yaohua Wang:
Matrix Odd-Even Partition: A High Power-Efficient Solution to the Small Grain Data Shuffle. NAS 2011: 348-354 - 2010
- [c1]Shenggang Chen, Shuming Chen, Huitao Gu, Hu Chen, Yaming Yin, Xiaowen Chen, Shuwei Sun, Sheng Liu, Yaohua Wang:
Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform. HPCC 2010: 465-470
Coauthor Index
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last updated on 2024-12-23 20:33 CET by the dblp team
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