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ORCIDSamy Meftali
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- affiliation: Université de Lille 1, France
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2020 – today
- 2024
[j14]Ali Dabba, Abdelkamel Tari, Samy Meftali:
A novel grey wolf optimization algorithm based on geometric transformations for gene selection and cancer classification. J. Supercomput. 80(4): 4808-4840 (2024)- 2023
- [j13]Ali Dabba
, Abdelkamel Tari, Samy Meftali:
A new multi-objective binary Harris Hawks optimization for gene selection in microarray data. J. Ambient Intell. Humaniz. Comput. 14(4): 3157-3176 (2023) - 2021
- [j12]Ali Dabba, Abdelkamel Tari, Samy Meftali, Rabah Mokhtari:
Gene selection and classification of microarray data method based on mutual information and moth flame algorithm. Expert Syst. Appl. 166: 114012 (2021) - [j11]Ali Dabba, Abdelkamel Tari, Samy Meftali:
Hybridization of Moth flame optimization algorithm and quantum computing for gene selection in microarray data. J. Ambient Intell. Humaniz. Comput. 12(2): 2731-2750 (2021) - 2020
- [j10]Hugo Sbai, Jassim Happa, Michael Goldsmith, Samy Meftali:
A survey on screenlogger attacks as well as countermeasures. Int. J. Embed. Syst. 12(4): 441-452 (2020) - [c29]Hugo Sbaï, Jassim Happa, Michael Goldsmith, Samy Meftali:
Dataset Construction and Analysis of Screenshot Malware. TrustCom 2020: 646-655
2010 – 2019
- 2019
- [j9]Ugo Sbai, Samy Meftali, Djamel Aouali:
An Optimal Allocation of Tracking Tasks in a SW/HW Fog/Cloud Based Distributed Video Surveillance System. J. Commun. 14(2): 159-163 (2019) - 2018
- [j8]Gilberto Ochoa-Ruiz, Pamela Wattebled, Maamar Touiza, Florent de Lamotte, El-Bay Bourennane, Samy Meftali, Jean-Luc Dekeyser, Jean-Philippe Diguet:
A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. J. Parallel Distributed Comput. 112: 1-19 (2018) - [c28]Hugo Sbai, Michael Goldsmith, Samy Meftali, Jassim Happa:
A Survey of Keylogger and Screenlogger Attacks in the Banking Sector and Countermeasures to Them. CSS 2018: 18-32 - 2014
- [c27]Chiraz Trabelsi, Samy Meftali, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Model-driven design flow for distributed control in reconfigurable FPGA systems. DASIP 2014: 1-6 - 2013
- [j7]Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. Integr. 46(4): 404-412 (2013) - [j6]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Decentralized control for dynamically reconfigurable FPGA systems. Microprocess. Microsystems 37(8-A): 871-884 (2013) - 2012
- [j5]Majdi Elhaji, Pierre Boulet, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
System level modeling methodology of NoC design from UML-MARTE to VHDL. Des. Autom. Embed. Syst. 16(4): 161-187 (2012) - [j4]Imran Rafiq Quadri, Abdoulaye Gamatié, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser:
Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. J. Syst. Archit. 58(5): 178-194 (2012) - [c26]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Semi-distributed Control for FPGA-based Reconfigurable Systems. DSD 2012: 185-192 - [c25]Gilberto Ochoa-Ruiz, Ouassila Labbani-Narsis, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser:
Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. ReConFig 2012: 1-8 - [c24]Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
Distributed control for reconfigurable FPGA systems: A high-level design approach. ReCoSoC 2012: 1-8 - [c23]Gilberto Ochoa-Ruiz, Ouassila Labbani, El-Bay Bourennane, Sana Cherif, Samy Meftali, Jean-Luc Dekeyser:
Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. RSP 2012: 107-113 - 2011
- [j3]Chiraz Trabelsi, Rabie Ben Atitallah, Samy Meftali, Jean-Luc Dekeyser, Abderrazek Jemai:
A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. EURASIP J. Embed. Syst. 2011 (2011) - [c22]Majdi Elhaji, Brahim Attia, Abdelkrim Zitouni, Rached Tourki, Samy Meftali, Jean-Luc Dekeyser:
FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. DASIP 2011: 269-276 - [c21]Sana Cherif, Chiraz Trabelsi, Samy Meftali, Jean-Luc Dekeyser:
High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. DASIP 2011: 308-315 - 2010
- [b2]Samy Meftali:
Vers la reconfiguration dynamique dans les systèmes embarqués: de la modélisation à l'implémentation. (Toward Dynamically Reconfigurable in Embedded Systems: From Models to Implementations). Lille University of Science and Technology, France, 2010 - [j2]Imran Rafiq Quadri, Huafeng Yu, Abdoulaye Gamatié, Éric Rutten, Samy Meftali, Jean-Luc Dekeyser:
Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. Int. J. Embed. Syst. 4(3/4): 204-224 (2010) - [c20]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. DASIP 2010: 68-75 - [c19]Sana Cherif, Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. DSD 2010: 706-713 - [c18]Majdi Elhaji, Abdelkrim Zitouni, Samy Meftali, Jean-Luc Dekeyser, Rached Tourki:
A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. ISSPIT 2010: 528-531
2000 – 2009
- 2009
- [j1]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
High level modeling of Dynamic Reconfigurable FPGAs. Int. J. Reconfigurable Comput. 2009: 408605:1-408605:15 (2009) - 2008
- [c17]Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser:
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. ESTIMedia 2008: 47-52 - [c16]Imran Rafiq Quadri, Pierre Boulet, Samy Meftali, Jean-Luc Dekeyser:
Using an MDE Approach for Modeling of Interconnection Networks. ISPAN 2008: 289-294 - 2007
- [c15]Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser:
Massively parallel processing on a chip. Conf. Computing Frontiers 2007: 277-286 - [c14]Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser:
An MPSoC Performance Estimation Framework Using Transaction Level Modeling. RTCSA 2007: 525-533 - 2006
- [c13]Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration. ARCS 2006: 298-310 - [c12]Rabie Ben Atitallah, Lossan Bonde, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser:
Multilevel MPSoC Performance Evaluation Using MDE Approach. SoC 2006: 1-4 - 2005
- [c11]Samy Meftali, Anouar Dziri, Luc Charest, Philippe Marquet, J. Deskeyser:
SOAP Based Distributed Simulation Environment for SoC Design. FDL 2005: 283-291 - [c10]J. Vennin, S. Penain, Luc Charest, Samy Meftali, Jean-Luc Dekeyser:
Embed Scripting inside SystemC. FDL 2005: 373-385 - [c9]Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson:
Scalable Multistage Network for Multiprocessor System-on-Chip Design. ISPAN 2005: 352-357 - 2004
- [c8]E. Turbatu, Samy Meftali, Smaïl Niar, Jean-Luc Dekeyser:
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). FDL 2004: 378-380 - [c7]M. Samyn, Samy Meftali, Jean-Luc Dekeyser:
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. FDL 2004: 452-463 - [c6]Samy Meftali, Jean-Luc Dekeyser:
SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. Virtual Enterprises and Collaborative Networks 2004: 387-394 - [c5]Samy Meftali, Jean-Luc Dekeyser:
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. IWSOC 2004: 55-58 - 2002
- [b1]Samy Meftali:
Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs mono puce = Architectures exploration and memory allocation/assignment in multiprocessor SoC. (Architectures exploration and memory allocation/assignment in multiprocessor SoC). Grenoble Institute of Technology, France, 2002 - [c4]Ferid Gharsalli, Samy Meftali, Frédéric Rousseau, Ahmed Amine Jerraya:
Automatic generation of embedded memory wrapper for multiprocessor SoC. DAC 2002: 596-601 - [c3]Ahmed Amine Jerraya, Damien Lyonnard, Samy Meftali, Frédéric Rousseau, Ferid Gharsalli:
Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. ISSS 2002: 26-31 - 2001
- [c2]Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya:
Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. VLSI-SOC 2001: 193-204 - [c1]Samy Meftali, Ferid Gharsalli, Frédéric Rousseau, Ahmed Amine Jerraya:
An optimal memory allocation for application-specific multiprocessor system-on-chip. ISSS 2001: 19-24
Coauthor Index
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