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ORCIDMichael Payer
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2000 – 2009
- 2003
[c9]Michael Payer:
A Platform for Construction and Integration of Digital IP Blocks. MBMV 2003: 131-131- 2001
- [j7]Michael Payer:
Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation). Informationstechnik Tech. Inform. 43(1): 16-21 (2001) - 2000
- [c8]Michael Payer:
Industrial Experience with Formal Verification. MBMV 2000: 9-16
1990 – 1999
- 1995
- [c7]Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl:
Model Checking in Industrial Hardware Design. DAC 1995: 298-303 - 1993
- [j6]Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy:
The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 244-253 (1993) - 1992
- [j5]Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Allocation algorithms based on path analysis. Integr. 13(3): 283-299 (1992) - [c6]Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer:
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274 - 1991
- [j4]Michael Payer:
Partitioning and ordering of CMOS circuits for switch level analysis. Integr. 10(2): 113-141 (1991) - [j3]Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Scheduling under resource constraints and module assignment. Integr. 12(1): 1-19 (1991) - [c5]Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Data-Path Synthesis Using Path Analysis. DAC 1991: 591-596 - [c4]Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer:
Area and performance optimizations in path-based scheduling. EURO-DAC 1991: 304-310
1980 – 1989
- 1989
- [b1]Michael Payer:
Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-Technik. University of Hamburg, Germany, 1989, pp. 1-233 - [c3]Michael Payer:
Finite State Machine Theory as a Tool for Construction of Systolic Arrays. EUROCAST 1989: 212-224 - 1988
- [j2]Reinhard H. Rauscher, Peter Kückendahl, Michael Payer:
A system for estimation of numerical stability for matrix operations in systolic arrays. Microprocess. Microprogramming 24(1-5): 527-534 (1988) - [c2]Michael Payer:
Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen. GI Jahrestagung (2) 1988: 174-190 - 1987
- [j1]Michael Payer:
Verification and validation of hierarchical CMOS gate array layouts. Microprocess. Microprogramming 21(1-5): 445-452 (1987) - 1980
- [c1]Michael Payer:
Systematischer Entwurf von Makroprozessoren. GI Jahrestagung 1980: 541
Coauthor Index
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