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Jörg Biesenack

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1990 – 1999

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1994
[c4]
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  - electronic edition @ acm.org
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  - conf/eurodac/WehnBDLMPR94
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  - https://dblp.org/rec/conf/eurodac/WehnBDLMPR94
Norbert Wehn, Jörg Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, Steffen Rumler:
Scheduling of behavioral VHDL by retiming techniques. EURO-DAC 1994: 546-551
1993
[j1]
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  - journals/tvlsi/BiesenackKLLMPPRSWD93
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Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy:
The Siemens high-level synthesis system CALLAS. IEEE Trans. Very Large Scale Integr. Syst. 1(3): 244-253 (1993)
1992
[c3]
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  - conf/eurodac/StollBR92
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A. Stoll, Jörg Biesenack, Steffen Rumler:
Flexible timing specification in a VHDL synthesis subset. EURO-DAC 1992: 610-615
[c2]
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Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer:
Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274
1991
[c1]
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  - conf/vlsi/WehnBP91
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Norbert Wehn, Jörg Biesenack, Michael Pilsl:
A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. VLSI 1991: 203-213

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