• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 17 matches

• 2000
• 
  Jeffrey Arnold, Wayne Luk, Ken Pocek:
  Guest Editors' Introduction. J. VLSI Signal Process. 24(2-3): 127 (2000)
• 
  Paul D. Fiore:
  Efficient Wordlength Reduction Techniques for DSP Applications. J. VLSI Signal Process. 24(1): 9-18 (2000)
• 
  Hugo de Garis, Michael Korkin:
  The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain. J. VLSI Signal Process. 24(2-3): 241-262 (2000)
• 
  Maya B. Gokhale, Janice M. Stone, Edson Gomersall:
  Co-Synthesis to a Hybrid RISC/FPGA Architecture. J. VLSI Signal Process. 24(2-3): 165-180 (2000)
• 
  Sangjin Hong, Wayne E. Stark:
  Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications. J. VLSI Signal Process. 24(1): 43-57 (2000)
• 
  Meenakshi Kaul, Ranga Vemuri:
  Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. J. VLSI Signal Process. 24(2-3): 181-209 (2000)
• 
  Richard P. Kleihorst, René J. van der Vleuten:
  DCT-Domain Embedded Memory Compression for Hybrid Video Coders. J. VLSI Signal Process. 24(1): 31-41 (2000)
• 
  Shiro Kobayashi, Gerhard P. Fettweis:
  A Hierarchical Block-Floating-Point Arithmetic. J. VLSI Signal Process. 24(1): 19-30 (2000)
• 
  Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves:
  Design and Implementation of the MorphoSys Reconfigurable Computing Processor. J. VLSI Signal Process. 24(2-3): 147-164 (2000)
• 
  Gaye Lightbody, Richard L. Walke, Roger F. Woods, John V. McCanny:
  Linear QR Architecture for a Single Chip Adaptive Beamformer. J. VLSI Signal Process. 24(1): 67-81 (2000)
• 
  Elias S. Manolakos, Wayne P. Burleson:
  Guest Editor's Introduction. J. VLSI Signal Process. 24(1): 5-6 (2000)
• 
  Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme:
  Application of Reconfigurable CORDIC Architectures. J. VLSI Signal Process. 24(2-3): 211-221 (2000)
• 
  Sydney Reader, Won Namgoong, Teresa H. Meng:
  Partitioning Analog and Digital Processing in Mixed-Signal Systems. J. VLSI Signal Process. 24(1): 59-65 (2000)
• 
  Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein:
  Pipeline Reconfigurable FPGAs. J. VLSI Signal Process. 24(2-3): 129-146 (2000)
• 
  Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis:
  A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models. J. VLSI Signal Process. 24(2-3): 223-240 (2000)
• 
  Andrew Stone, Elias S. Manolakos:
  DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. J. VLSI Signal Process. 24(1): 99-120 (2000)
• 
  Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
  Multidimensional Exploration of Software Implementations for DSP Algorithms. J. VLSI Signal Process. 24(1): 83-98 (2000)