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2020 – today
- 2023
[i1]Andrew Stone, Mustapha Aïssaoui, Samuel Sidor, Siva Sivabalan:
Local Protection Enforcement in the Path Computation Element Communication Protocol (PCEP). RFC 9488: 1-9 (2023)
2010 – 2019
- 2013
- [c10]Andrew Stone, Michelle Mills Strout:
Abstractions to separate concerns in semi-regular grids. ICS 2013: 3-12 - [c9]Christopher D. Krieger, Michelle Mills Strout, Catherine Olschanowsky, Andrew Stone, Stephen M. Guzik, Xinfeng Gao, Carlo Bertolli, Paul H. J. Kelly, Gihan R. Mudalige
, Brian van Straalen, Samuel Williams:
Loop Chaining: A Programming Abstraction for Balancing Locality and Parallelism. IPDPS Workshops 2013: 375-384 - 2012
- [c8]Andrew Stone, Michelle Mills Strout:
Abstractions for Defining Semi-Regular Grids Orthogonally from Stencils. LCPC 2012: 273-274 - [c7]Andrew Stone, John M. Dennis, Michelle Strout:
Establishing a Miniapp as a programmability proxy. PPoPP 2012: 333-334
2000 – 2009
- 2009
- [j3]Andrew Stone, Michelle Strout, Shweta Behere:
May/must analysis and the DFAGen data-flow analysis generator. Inf. Softw. Technol. 51(10): 1440-1453 (2009) - 2008
- [c6]Andrew Stone, Michelle Strout, Shweta Behere:
Automatic Determination of May/Must Set Usage in Data-Flow Analysis. SCAM 2008: 153-162 - 2007
- [c5]Peter Sawyer, Ricardo Gacitúa, Andrew Stone:
Profiling and Tracing Stakeholder Needs. Monterey Workshop 2007: 196-213 - 2006
- [j2]Andrew Stone, Peter Sawyer:
Identifying tacit knowledge-based requirements. IEE Proc. Softw. 153(6): 211-218 (2006) - [c4]Andrew Stone, Peter Sawyer:
Using pre-requirements tracing to investigate requirements based on tactic knowledge. ICSOFT (1) 2006: 139-144 - [c3]Andrew Stone, Peter Sawyer:
Exposing Tacit Knowledge via Pre-Requirements Tracing. RE 2006: 346-347 - 2000
- [j1]Andrew Stone, Elias S. Manolakos:
DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. J. VLSI Signal Process. 24(1): 99-120 (2000) - [c2]Andrew Stone, Elias S. Manolakos:
Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis. ASAP 2000: 92-102
1990 – 1999
- 1999
- [c1]John Bonk, Andrew Stone, Elias S. Manolakos:
Synthesis of array architectures for block matching motion estimation: design exploration using the tool DG2VHDL. ICASSP 1999: 1925-1928
Coauthor Index
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